Clock Generation : FPGA

Hi I am using Spartan-3 fpga

I need to generate 35.328 MHz clock

I have an external xtal of 35.328 MHz feeding to FPGA.

From this clock i need to generate 35.328 MHz square wave with fine resolution.

We need a resolution of 1Hz, that means i should be able to change the square wave out put frequency by 1 Hz resolution.

I tried to generate this by using DDS core provided by core-generator and taking the MSBit of the sine wave samples given by the DDS. But the spurious components generated using this method is too much for my application to accept.

Is there any-other way out ?

( This is for ADSL Modem appliaction. we currently use DDS provided by Analog devices.

So i thought of using FPGA for this purpose as an alternative solution. )

Thanks bijoy

bijoy wrote:

> Hi I am using Spartan-3 fpga
> 
> I need to generate 35.328 MHz clock
> 
> I have an external xtal of 35.328 MHz feeding to FPGA.
> 
> From this clock i need to generate 35.328 MHz square wave with fine resolution.
> 
> We need a resolution of 1Hz, that means i should be able to change the square wave out put frequency by 1 Hz resolution.
> 
> I tried to generate this by using DDS core provided by core-generator and taking the MSBit of the sine wave samples given by the DDS. But the spurious components generated using this method is too much for my application to accept.
> 
> Is there any-other way out ?
> 
> ( This is for ADSL Modem appliaction. we currently use DDS provided by Analog devices.
> 
> So i thought of using FPGA for this purpose as an alternative solution. )

How would an FPGA be able to achieve a clock that
was difficlt to achieve otherwise ? So when a 300MHz
DDS is too noisy, rebuilding the DDS with an FPGA
is not going to help.
What is also not going to help is a PLL with a Phase
comparator running at 1Hz.
The other possible way would be to single side band
modulate your carrier. The probelm there ist the
suppression of the other sideband and the suppression
of the carrier. In the 35MHz range, a suppression of
40dB should be doable. The existing 35MHz clock would
be the LO, of which you'd need another channel 90
degrees shifted. Then you's need the difference frequency,
in 1Hz steps, possibly from a DDS, and a pair of
mixers. This difference frequency is the IF channel,
also required in quadrature, eg 90 degrees shifted.

I'd stick with a DSS and filter the signal.
An AD9854 or such.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Hi Rene We are presently using AD9854 but it is too costly for a USB ADSL2+ modem

So i was searching for alternatives. Thats how i reached DDS on FPGA which generates sine wave samples and take the MSbit to generate square wave, that is what found to be noisy.

bijoy

If you start off with a much higher frequency clock, the MSbit from a 
DDS that produces a phase output (no need to generate a sine if all 
you're using is the MSbit) won't be as noisy.  In the time domain, the 
DDS jitter will be up to 1 master clock period, peak-to-peak.  The clock 
can be cleaned up with an external 0 delay buffer as long as all the 
generated spurs are high in frequency, reducing your jitter to a 25 ps 
class device.  The 0 delay buffer isn't $1.  A DDS run by a multiple of 
35.328 MHz generating 35.328001 MHz will produce an unfilterable 1 Hz 
spur.  The trick is to find something where the tuning range is all high 
frequency jitter content.

There are plenty of techniques to get extreme precision but they aren't 
cheap.  Consider that the noise of a cheap crystal oscillator will 
probably wander around the 1 Hz resolution by several Hz depending on 
temperature, mood, microphonics, and other environmental effects.

Your specs may need to be reconsidered.

bijoy wrote:
> Hi I am using Spartan-3 fpga
> 
> I need to generate 35.328 MHz clock
> 
> I have an external xtal of 35.328 MHz feeding to FPGA.
> 
> From this clock i need to generate 35.328 MHz square wave with fine resolution.
> 
> We need a resolution of 1Hz, that means i should be able to change the square wave out put frequency by 1 Hz resolution.
> 
> I tried to generate this by using DDS core provided by core-generator and taking the MSBit of the sine wave samples given by the DDS. But the spurious components generated using this method is too much for my application to accept.
> 
> Is there any-other way out ?
> 
> ( This is for ADSL Modem appliaction. we currently use DDS provided by Analog devices.
> 
> So i thought of using FPGA for this purpose as an alternative solution. )
> 
> Thanks bijoy

bijoy wrote:
> Hi Rene We are presently using AD9854 but it is too costly for a USB ADSL2+ modem
> 
> So i was searching for alternatives. Thats how i reached DDS on FPGA which generates sine wave samples and take the MSbit to generate square wave, that is what found to be noisy.

Ok, another lower cost alternative could be running two PLLs.
There are these ADF4001 for 8$ @100, they operate between 10
and 200MHz. So by taking one as reference for a second...
One would have to play with the numbers.
Or two of them plus a CPLD. I remeber an article recently
that they were achieving rather low difference frequencies.
Yep, the article was about how to generate a second
frequency very close to the original for sampling purposes.
But without long integeration times in the PLLs.
I'll look it up.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

"John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag
news:tPDne.35062$GN3.17984@trnddc04...

> > I need to generate 35.328 MHz clock
> >
> > I have an external xtal of 35.328 MHz feeding to FPGA.
> >
> > From this clock i need to generate 35.328 MHz square wave with fine
resolution.
> >
> > We need a resolution of 1Hz, that means i should be able to change the
square wave out put frequency by 1 Hz resolution.

Hmm, how about using a cheap VCO based PLL (ala 4046) and a DDS (inside the
FPGA) generating lets say 3.5328 MHz. Multiply the 35.328 by four. Run the
DDS at this frequency, a 32 bit accu will give a resolution of  0,03 Hz. Use
the analog PLL to multiply by ten. This way your frequency resolution is
degraded to 0,3 Hz, but this sounds enough for your application. If the loop
filter is designed properly the broadband/high frequency jitter is filtered
out.

Regards
Falk

Average frequency resolution is trivial with DDS.
I recently built a box that generates 1 Hz to 640 MHz in 1 Hz
increments
( and 1 mHz would have meant just another ten stages in the
accumulator.)
The issue is jitter and stability or "wander".
The DDS gives you a whole clock period of systematic and deterministic
jitter.
So that's a couple of nanoseconds plus the original clock jitter plus
DCM jitter.
Then you can play all sorts of tricks to reduce the jitter,
but don't expect to get below 50 ps of cycle-to-cycle jitter for any
adjustable frequency.
(Fixed frequency generators with high-Q resonators are a different
thing)
Agilent can barely get below 40 ps, and they have 60+ years of
experience, and charge thousands of dollars...

Then figure out the instantaneous frequency stability:
50 ps @ 100 MHz = 50 parts in 10,000 = 1 part in 200 = 500 kHz
"sidebands".
Things get really ugly when you move between the frequency and the time
domain.  :-(
Peter Alfke, Xilinx Applications

Falk Brunner wrote:
> "John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag
> news:tPDne.35062$GN3.17984@trnddc04...
>
> > > I need to generate 35.328 MHz clock
> > >
> > > I have an external xtal of 35.328 MHz feeding to FPGA.
> > >
> > > From this clock i need to generate 35.328 MHz square wave with fine
> resolution.
> > >
> > > We need a resolution of 1Hz, that means i should be able to change the
> square wave out put frequency by 1 Hz resolution.
>
> Hmm, how about using a cheap VCO based PLL (ala 4046) and a DDS (inside the
> FPGA) generating lets say 3.5328 MHz. Multiply the 35.328 by four. Run the
> DDS at this frequency, a 32 bit accu will give a resolution of  0,03 Hz. Use
> the analog PLL to multiply by ten. This way your frequency resolution is
> degraded to 0,3 Hz, but this sounds enough for your application. If the loop
> filter is designed properly the broadband/high frequency jitter is filtered
> out.
> 
> Regards
> Falk

At 35 MHz, the period is around 30 ns.
If you change the frequency by 1 Hz, you change the period by 30 ns /
35 million.
That is less than one femtosecond. (Less than a thousandth of a
picosecond)
Light travels 0.3 micron (about half its own wave length) in 1
femtosecond.
Just to put things in perspective...
Peter Alfke

At 35 MHz, the period is around 30 ns.
If you change the frequency by 1 Hz, you change the period by 30 ns /
35 million.
That is less than one femtosecond. (Less than a thousandth of a
picosecond)
Light travels 0.3 micron (about half its own wave length) in 1
femtosecond.
Just to put things in perspective...
Peter Alfke

Hi Falk

I did not get your idea ..

Could you please put ur idea in a figure please ..

to interface VCO to DDS shall we need a DAC also ?

regards bijoy