Measuring DDR SDRAM

Hi,

maybe someone has had any experience on the following problem:

I am searching for guidelines on measuring data lines, strobe lines,
control lines
between DDR SDRAM and user FPGAs (DDR SDRAM controller) on the board
but unfortunately I have not found such information yet.

I would like to know what I have to take into account when trying to
measure with an oscilloscope the different data lines so that data
integrity is not negatively affected.

Are there any layout guidelines/examples/papers for adding measuring
points (for example approach with coaxial connectors) to the DDR lines
?

What bandwidths do you recommend for oscilloscopes when measuring
phases between
DQ and DQS for 133MHz reliably?

Thank you for your help in advance.

Rgds
Andr=E9