[Vir2] Can I use a 18k ram as 2 single-port ram?

Hi all,

I use Xilinx Vertex2 FPGA. Can I use a 18k ram as 2 single-port ram?

Best regards,
Davy

You have two independent access mechanism, but only one 18Kb storage
area.
If you want two separate single-portRAMs, you must assure that the two
ports never overlap into the storage area.
The simplest way is to tie one address bit in one port High, and the
SAME addresss bit on the other port low. That gives you two independent
9Kb RAMs, but you might also divide less symmetriclly.
Once you realize: two completely independent access mechanism, but one
common storage area, the rest is obvious.
Peter Alfke, Xilinx Applications

Hi Mr.Alfke,

Could 2 single-port RAM be accessed at the same time?

Best regards,
Davy

Hi Davy,

  > Could 2 single-port RAM be accessed at the same time?

  short answer: yes - as Peter already explained:

  >> two completely independent access mechanism, [...]

Jochen

Davy,

Just to complemenmt what Peter and Jochen said, as you go simulating your 
memory,
remember that write and read to the same address entry will give you unknown 
values.
you will have to bypass this.

Vladislav

"Davy" <zhushenli@gmail.com> wrote in message 
news:1118280314.768895.81260@z14g2000cwz.googlegroups.com...
> Hi all,
>
> I use Xilinx Vertex2 FPGA. Can I use a 18k ram as 2 single-port ram?
>
> Best regards,
> Davy
> 

Hi Davy,
just to let you know that i did exactly the same thing recently.
I split the Dual Port Rams into 2 with independent access control.
The simulation was perfect. Try it ...its quite simple when you think about
it.
Good Luck,
Adarsh
"Davy" <zhushenli@gmail.com> wrote in message
news:1118311830.368908.11780@g14g2000cwa.googlegroups.com...
> Hi Mr.Alfke,
>
> Could 2 single-port RAM be accessed at the same time?
>
> Best regards,
> Davy
>

Vladislav, what you wrote is correct, but totally irrelevant to this
thread.
Once you divide the memory into two, you can do anything you want in
the two memories.
The problem you mention only occurs when you do NOT separate the memory
between the two ports.
Peter Alfke

As Peter points out, by splitting the memory into 2 independent blocks,
there is no way in which you should see the problem which Vladislav 
mentions, if you have done your splitting correct and the control of the 
address lines is designed correctly.
i recently had to go through all this, as i had to implement a design 
which needed more than the number of BRAMs i had on my Xilinx and since 
the size requirements were
such that i could fit 4 of my memories into one BRAM(which would have 
been great..but alas not possible...), i split all the RAMs i had, into 
two, in this way.
I was also wondering if people do this with Dual Port Rams often ?
adarsh

Peter Alfke wrote:
> Vladislav, what you wrote is correct, but totally irrelevant to this
> thread.
> Once you divide the memory into two, you can do anything you want in
> the two memories.
> The problem you mention only occurs when you do NOT separate the memory
> between the two ports.
> Peter Alfke
> 

As Peter points out, by splitting the memory into 2 independent blocks,
there is no way in which you should see the problem which Vladislav
mentions, if you have done your splitting correct and the control of the
address lines is designed correctly.
i recently had to go through all this, as i had to implement a design which
needed more than the number of BRAMs i had on my Xilinx and since the size
requirements were
such that i could fit 4 of my memories into one BRAM(which would have been
great..but alas not possible...), i split all the RAMs i had, into two, in
this way.
I was also wondering if people do this with Dual Port Rams often ?
adarsh




"Peter Alfke" <alfke@sbcglobal.net> wrote in message
news:1118327246.775542.254240@f14g2000cwb.googlegroups.com...
> Vladislav, what you wrote is correct, but totally irrelevant to this
> thread.
> Once you divide the memory into two, you can do anything you want in
> the two memories.
> The problem you mention only occurs when you do NOT separate the memory
> between the two ports.
> Peter Alfke
>

If you like living dangerously, you can allow the full address space on
both ports, run the addresses on one port in ascending order starting
at 0, on the other port in descending order starting at max, and MAKE
SURE that the two addresses NEVER overlap...
That could even make the partition adaptive. Clever, but not for the
faint-of-heart.

Peter Alfke, Xilinx Applications