"Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag news:1118333386.904961.64570@g43g2000cwa.googlegroups.com...> If you like living dangerously, you can allow the full address space on > both ports, run the addresses on one port in ascending order starting > at 0, on the other port in descending order starting at max, and MAKE > SURE that the two addresses NEVER overlap... > That could even make the partition adaptive. Clever, but not for the > faint-of-heart.Hmm. Same risk level as every stack on every processor (unless memory protection can avoid the stack reaching data storage places) Regards Falk
[Vir2] Can I use a 18k ram as 2 single-port ram?
Started by ●June 8, 2005
Reply by ●June 9, 20052005-06-09
Reply by ●June 12, 20052005-06-12
Hi all, There is another question: Why Xilinx designed 18k ram? 18k isn't 2^n. How to seperate its address into "1XX...XX" and "0XX...XX"? Best regards, Davy
Reply by ●June 12, 20052005-06-12
"Davy" <zhushenli@gmail.com> schrieb im Newsbeitrag news:1118562757.483278.159870@g43g2000cwa.googlegroups.com...> Hi all, > > There is another question: Why Xilinx designed 18k ram? 18k isn't 2^n. > How to seperate its address into "1XX...XX" and "0XX...XX"?It has additional bit lanes for extra use, like parity, control, whatever. It can be configured as 16k x1 8k x 2 4k x 4 2k x 9 1k x 18 0.5k x 36 Regards Falk
Reply by ●June 12, 20052005-06-12
Hi Mr.Brunner, Thank you for your help! And if I want two 8k ram in one 18k ram, how to declear this situation? And can nine 2k or four 4k ram in one 18k ram be access at the same time? Best regards, Davy
Reply by ●June 12, 20052005-06-12
> And if I want two 8k ram in one 18k ram, how to declear this situation?8k and 18k isnt a clean statement. How wide shall the RAMs be? 1 bit? 32 Bit? You can use CoreGen to get a full configured macro, fit to your settings. Or you can use the templates from the VHDL template wizard and wire them up on your own.> And can nine 2k or four 4k ram in one 18k ram be access at the same > time???? There are multiple RAM block inside the FPGA. every block can be accessed individually. Even more, since they are true dual ported, you can access each port on every BlockRAM individually. Regards Falk
Reply by ●June 12, 20052005-06-12
On Thu, 9 Jun 2005 09:20:07 -0400, "Vladislav Muravin" <muravinv@advantech.ca> wrote:>Davy, > >Just to complemenmt what Peter and Jochen said, as you go >simulating your memory, >remember that write and read to the same address entry >will give you unknown values. you will have to bypass this. >VladislavActually, the situation of both ports accessing the same address is somewhat more complex than "it never works" . I described it here: http://www.fpga-faq.com/archives/72650.html#72651 Philip Freidin Fliptronics
Reply by ●June 12, 20052005-06-12
On 12 Jun 2005 00:52:37 -0700, "Davy" <zhushenli@gmail.com> wrote:>Hi all, > >There is another question: Why Xilinx designed 18k ram? 18k isn't 2^n.The Xilinx BRAM has configurable width. When it is 1, 2, or 4 bits wide, the depths are 16K, 8K, and 4K respectively. All deliver 16K bits total. I.E. in 4 bit wide mode, the memory has 4K locations, and each read or write transfers 4 bits at a time. For 8 and 16 bits wide, there is an extra bit for each 8 bits, so the widths are really 9 or 18 bits, and the depths are 2K and 1K respectively. I.E. in 18 bit wide mode, the memory is 1K deep, for a total of 18K bits, and reads and writes transfer 18 bits at a time. "Why is it designed this way?" you ask. The optimal size for on chip block rams is 16K bits, although the organization (width by depth is scattered among the 5 different arrangements I have just described). 2K bytes holds a standard length ethernet packet (1.5K), A line of video from a high res screen (1600 pixels), (or maybe multiple blocks for RGB) A reasonable amount of a track of a disk drive, A CPU cache that isn't trivially small, and lots of other things. Since you can gang them together, that lets you build bigger structures. Either wider, or deeper, or both. Since you can use them separately, you can have enormous on chip bandwidth that you would not get if you built a smaller number of larger blocks. In the grand scheme of things, 16K bits covers the most possible applications efficiently, especially if it is also dual port, and hopefully synchronous. If you asked designers whether the memory should include parity, a high percentage would say that it is mandatory. So that makes the 8 and 16 bit widths, 9 and 18. When you actually look at what designers do with the memories at 9 and 18 bits width, almost none use the extra bit for parity. But is is heavilly used for tag/flag type info. For example, if you built a FIFO with block RAM, and you had a stream of packets that were each 53 bytes long (an ATM packet), you could set the 9th bit on the first byte of the packet as you store it into the FIFO, and when you were reading out of the FIFO, there it would be to differentiate a start of packet from the rest of the packet.>How to seperate its address into "1XX...XX" and "0XX...XX"?So the only time the memory is 18K bits is for by 9 and by 18 width. At by 9, the depth is 2K, or 11 address bits, and all the addresses are valid. Similarly, for 18 bit wide mode there are 10 address bis, and all addresses are valid.>Best regards, >DavyCheers, Philip =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORG
Reply by ●June 13, 20052005-06-13
I would also like to recommend the following application note. It covers many of these details. Although it's written for Spartan-3-3E, it applies equally well to Virtex-II and Virtex-II Pro. XAPP463: Using Block RAM in Spartan-3 Generation FPGAs http://www.xilinx.com/bvdocs/appnotes/xapp463.pdf --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs E-mail: steve.knapp@xilinx.com --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs. "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:3h2emnFems79U1@individual.net...> > > And if I want two 8k ram in one 18k ram, how to declear this situation? > > 8k and 18k isnt a clean statement. How wide shall the RAMs be? 1 bit? 32 > Bit? > You can use CoreGen to get a full configured macro, fit to your settings.Or> you can use the templates from the VHDL template wizard and wire them upon> your own. > > > And can nine 2k or four 4k ram in one 18k ram be access at the same > > time? > > ??? > There are multiple RAM block inside the FPGA. every block can be accessed > individually. Even more, since they are true dual ported, you can access > each port on every BlockRAM individually. > > Regards > Falk > > >
