5 Volt tolerance - Altera

I am using a MAX II part in a new design with 3.3V supplies.

I understand why the inputs might not be 5 volt tolerant.

Altera states that the outputs are not 5 volt tolerant when driving CMOS 
but are OK for TTL. Since TTL is essentially dead, I'm not sure this is of 
any real benefit, however this is not my main concern.

I don't see why there would be any problem driving a CMOS input provided 
that the CMOS input will accept 3.3V signals as high. There certainly isn't 
going to be any significant current flow into the CMOS gate. 

I think this situation is similiar for a number of FPGAs as well.

Could someone enlighten me as to the reasons why, instead of Altera's 
"because we said so" 


-- 
Al Clark
Danville Signal Processing, Inc.
--------------------------------------------------------------------
Purveyors of Fine DSP Hardware and other Cool Stuff
Available at http://www.danvillesignal.com

This is the case of very cautious worst-case specifications.

If the CMOS output is truly complementary (most of them are nowadays),
and there is no pulldown load, Voh will in reality be exactly = Vcc
(although the specification will probably mention a lower value.)
So Voh min = 3.0 V or slightly higher.

A True CMOS input has an input threshold around 40 to 60% of Vcc ( or
30 to 70%), and Vcc might be as high as 5.5 V So the input threshold
might be well above 3 V.
Now you see that this interface does not work "worst case"

If the CMOS input is called TTL (just an indication of input threshold,
no other realtion to the bipolar TTL technology), then the input
threshold is artificially made much lower, around 1.5 V, and the
interface works perfectly.
Clear?
Peter Alfke, Xilinx Applications

Hi,

I think the important distinction to make is the distinction between TTL
signaling levels and TTL parts.  I see many people (including myself) who
use "TTL" and "seventy four hundred series devices" interchangably.

> I don't see why there would be any problem driving a CMOS input provided
> that the CMOS input will accept 3.3V signals as high. There certainly
isn't
> going to be any significant current flow into the CMOS gate.

What you cite is exactly the issue.  If a 5.0v CMOS device has a Vih,min
that is 90% of the 5.0v supply rail, your programmable logic device output
isn't going to satisfy the requirement -- because it will only be able to
pull up to 3.3v.

Counterpoint, consider a 5.0v TTL device, where the Vih,min might be around
2.4 volts.  Your programmable logic device will be able to pull up higher
than what is required, so it will work properly.

At the end of the day, the best advice I can offer you is to read the
datasheets of both parts and carefully consider the signaling levels and
thresholds, and don't forget to design for some noise margin.

Eric

"Peter Alfke" <peter@xilinx.com> wrote in news:1119307329.734267.74850
@f14g2000cwb.googlegroups.com:

> This is the case of very cautious worst-case specifications.
> 
> If the CMOS output is truly complementary (most of them are nowadays),
> and there is no pulldown load, Voh will in reality be exactly = Vcc
> (although the specification will probably mention a lower value.)
> So Voh min = 3.0 V or slightly higher.
> 
> A True CMOS input has an input threshold around 40 to 60% of Vcc ( or
> 30 to 70%), and Vcc might be as high as 5.5 V So the input threshold
> might be well above 3 V.
> Now you see that this interface does not work "worst case"
> 
> If the CMOS input is called TTL (just an indication of input threshold,
> no other realtion to the bipolar TTL technology), then the input
> threshold is artificially made much lower, around 1.5 V, and the
> interface works perfectly.
> Clear?
> Peter Alfke, Xilinx Applications
> 

Hi,

I think the important distinction to make is the distinction between TTL
signaling levels and TTL parts.  I see many people (including myself) who
use "TTL" and "seventy four hundred series devices" interchangably.

> I don't see why there would be any problem driving a CMOS input 
provided
> that the CMOS input will accept 3.3V signals as high. There certainly
isn't
> going to be any significant current flow into the CMOS gate.

What you cite is exactly the issue.  If a 5.0v CMOS device has a Vih,min
that is 90% of the 5.0v supply rail, your programmable logic device 
output
isn't going to satisfy the requirement -- because it will only be able to
pull up to 3.3v.

Counterpoint, consider a 5.0v TTL device, where the Vih,min might be 
around
2.4 volts.  Your programmable logic device will be able to pull up higher
than what is required, so it will work properly.

At the end of the day, the best advice I can offer you is to read the
datasheets of both parts and carefully consider the signaling levels and
thresholds, and don't forget to design for some noise margin.

Eric



Thanks Peter & Eric,

This explanation makes perfect sense to me now. I understand that my CMOS 
inputs need to interpret a nominal 3.3 V level reliably as a logic high 
signal level. This is usually the case with the devices I will be 
interfacing with.  

I think Altera could have clearly stated this in their manuals or web 
site as well (perhaps Xilinx does).

-- 
Al Clark
Danville Signal Processing, Inc.
--------------------------------------------------------------------
Purveyors of Fine DSP Hardware and other Cool Stuff
Available at http://www.danvillesignal.com

On Mon, 20 Jun 2005 22:07:52 GMT, Al Clark <dsp@danvillesignal.com> wrote:

>I am using a MAX II part in a new design with 3.3V supplies.
>
>I understand why the inputs might not be 5 volt tolerant.
>
>Altera states that the outputs are not 5 volt tolerant when driving CMOS 
>but are OK for TTL. Since TTL is essentially dead, I'm not sure this is of 
>any real benefit, however this is not my main concern.

TTL is dead but HC and AC logic is available with TTL input levels (HCT/ACT), which you will need to
use if driving from 3.3v logic.

> I am using a MAX II part in a new design with 3.3V supplies.
> I understand why the inputs might not be 5 volt tolerant.

Be careful with your terms.  5 volt tolerant means that the device can
survice and operate connected to other 5 volt devices.  Typically it's
used when a 3.3 or lower voltage device is connected to a 5 volt device
and means that the 5 vold device won't damage the 3.3 volt device.

5 volt compatible means that the 3.3 volt device will receive and
transmit 5 volt voltage levels ignals.  TTL compatible means TTL signal
levels and CMOS compatible means CMOS voltage levels

> Altera states that the outputs are not 5 volt tolerant when driving CMOS
> but are OK for TTL. Since TTL is essentially dead, I'm not sure this is of
> any real benefit, however this is not my main concern.

Change your word tolerant to compatible and perhaps your sentence
becomes clearer.

> I don't see why there would be any problem driving a CMOS input provided
> that the CMOS input will accept 3.3V signals as high. There certainly isn't
> going to be any significant current flow into the CMOS gate.

Hope this helped.

gm

"GMM50" <george.martin@att.net> wrote in
news:1119375054.622966.257160@o13g2000cwo.googlegroups.com: 

>> I am using a MAX II part in a new design with 3.3V supplies.
>> I understand why the inputs might not be 5 volt tolerant.
> 
> Be careful with your terms.  5 volt tolerant means that the device can
> survice and operate connected to other 5 volt devices.  Typically it's
> used when a 3.3 or lower voltage device is connected to a 5 volt
> device and means that the 5 vold device won't damage the 3.3 volt
> device. 
> 
> 5 volt compatible means that the 3.3 volt device will receive and
> transmit 5 volt voltage levels ignals.  TTL compatible means TTL
> signal levels and CMOS compatible means CMOS voltage levels
> 
>> Altera states that the outputs are not 5 volt tolerant when driving
>> CMOS but are OK for TTL. Since TTL is essentially dead, I'm not sure
>> this is of any real benefit, however this is not my main concern.
> 
> Change your word tolerant to compatible and perhaps your sentence
> becomes clearer.
> 
>> I don't see why there would be any problem driving a CMOS input
>> provided that the CMOS input will accept 3.3V signals as high. There
>> certainly isn't going to be any significant current flow into the
>> CMOS gate. 
> 
> Hope this helped.
> 
> gm
> 
> 

I don't have any issue with your terminology. I think the reason I 
suggested 5 volt tolerant was because Altera goes to great length talking 
about pullup resistors and clamping diodes for output signals which 
implied that there might be a "tolerance issue" . 

I think that Altera could have been clearer by stating that the part can 
drive TTL compatible inputs rather than simply stating TTL. TTL parts are 
members of families such as the 74LS. TTL compatible are parts like the 
members of the 74HCT family (and many others).   

All Altera really needed to do was discuss the Vih threshold issue in the 
first place.





-- 
Al Clark
Danville Signal Processing, Inc.
--------------------------------------------------------------------
Purveyors of Fine DSP Hardware and other Cool Stuff
Available at http://www.danvillesignal.com

Al Clark wrote:
>
> All Altera really needed to do was discuss the Vih threshold issue in the
> first place.
>

I think Altera's part in this issue is to tell you about the device,
and not to educate you !

Karl.

Actually the bigger issue with 5V tolerance is how the 3V part
tolerates
5V input signals - this is one of the nice features of (some of) the
Coolrunners
which I use.
Driving 5V logic from 3V should be no issue - as it was mentioned,
HCT, ACT etc. parts have been available for > a decade.
However, it should be noted that "TTL compatible" output means
more than just guaranteeing output voltage >2.4V for 1 and < 0.4V for
0;
it means being able to sink 1.6 mA and to source 400 uA (all out of
memory older than 15 years, hope I got it right).

Dimiter

-------------------------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments
http://www.tgi-sci.com
-------------------------------------------------------------------------

Sinking 1.6 mA and sourcing 400 uA is a very easy task for modern CMOS
outputs. they are usually specified for much higher currents (or lower
output resistance).
The bigger input issue is: what happend when the input is driven High.
Many CMOS pins have a diode directly connected to their Vcc, which will
be driven to conducting current by any input voltage above 4 V ( or
even 3.6 V at extremes). That's where the 100 Ohm
current-limiting-resistor idea comes from.
Peter Alfke