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DC Offset removal in FPGA

Started by Unknown June 23, 2005
Hi,

we are reading an ADC o/p through FPGA. To remove the DC Offset present
in the ADC input we have a DAC which can remove this DC offset using a
subtractor before the actual analog input (with added DC offset) goes
to ADC.

Now I want my FPGA to calculate the DC offset from ADC outputs and then
feed this value to DAC input which in turn cancel the DC offset using
subtrator.

can anybody suggest me how can i implement this in FPGA? I just gone
through net and realized that i can use a subtractor and a MAC. The ADC
output will go to this Subtractor which has the final output of MAC as
other input. the subtractor output will be multiplied with some small
value K (??) and then an accumulator. The final output of accumulator
can be feedback to the DAC. The DAC o/p is going to Mixer to cancel the
DC offset?

this is what i understood. can somebody through some light?

suggestions are welcome.

Hi,
How would you do this in terms of analog electronics?
To separate the DC part from the mixed signal you have to generate an 
average of the AC/DC signal. This can be done with a low pass filter.

Low pass filters can also be implemented digitally. Depending on the 
required accuracy of your application the algorithm can be more or less 
complex/accurate.
Maybe your FPGA vendor offers some free macro blocks for IIR or FIR 
filters, where you only have to feed the coefficients for the desired 
filter characteristics. (e.g. Xilinx Coregen modules) so you don't have 
to reinvent it.

What you described (Subtractor and MAC) sounds more like an moving 
average algorithm. Maybe this will work for your application, but if you 
need higher accuracy and a defined frequency curve you need a real low 
pass filter.

Of course, the DC elimination can be done without the DAC, directly on 
the digital side of your design, (simply delay your input signal(e.g. 
shift register), and subtract the calculated DC value.

If you try to increase the dynamic resulution of your system (measuring 
a small ac signal with high resolution on top of a larger DC signal) you 
may need your approach, but please consider if the system may become 
cheaper or easyer to manufacture if you just use a ADC with some more 
bits of resolution and do the digital subtraction method?

have a nice synthesis
   eilert    backhus(�t)isms_punkt_hs-bremen_punkt_de

   "punkt" is german for dot


shridhar@mistralsoftware.com schrieb:
> Hi, > > we are reading an ADC o/p through FPGA. To remove the DC Offset present > in the ADC input we have a DAC which can remove this DC offset using a > subtractor before the actual analog input (with added DC offset) goes > to ADC. > > Now I want my FPGA to calculate the DC offset from ADC outputs and then > feed this value to DAC input which in turn cancel the DC offset using > subtrator. > > can anybody suggest me how can i implement this in FPGA? I just gone > through net and realized that i can use a subtractor and a MAC. The ADC > output will go to this Subtractor which has the final output of MAC as > other input. the subtractor output will be multiplied with some small > value K (??) and then an accumulator. The final output of accumulator > can be feedback to the DAC. The DAC o/p is going to Mixer to cancel the > DC offset? > > this is what i understood. can somebody through some light? > > suggestions are welcome. >
You might find some good reading at http://tinyurl.com/chz9s which can 
also be found with:

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=kc_dig_offset&languageID=1

The techXclusive article goes through dc offset removal in some detail 
but doesn't cover your explicit technique of analog feedback as far as I 
recall.  Your method seems sound as long as you 1) properly lowpass the 
DAC feedback and use an integrator (or accommodate the offset feedback 
in the digital part of the loop) since the feedback will result in 0 DC 
offset.


shridhar@mistralsoftware.com wrote:
> Hi, > > we are reading an ADC o/p through FPGA. To remove the DC Offset present > in the ADC input we have a DAC which can remove this DC offset using a > subtractor before the actual analog input (with added DC offset) goes > to ADC. > > Now I want my FPGA to calculate the DC offset from ADC outputs and then > feed this value to DAC input which in turn cancel the DC offset using > subtrator. > > can anybody suggest me how can i implement this in FPGA? I just gone > through net and realized that i can use a subtractor and a MAC. The ADC > output will go to this Subtractor which has the final output of MAC as > other input. the subtractor output will be multiplied with some small > value K (??) and then an accumulator. The final output of accumulator > can be feedback to the DAC. The DAC o/p is going to Mixer to cancel the > DC offset? > > this is what i understood. can somebody through some light? > > suggestions are welcome.
The TechXclusive paper by Ken chapman...suggested by John_H is the best
to tackle your problem. I used it to design my dc-cancellation ckt. It
works.
Def use the paper to design...unless you have a better solution..let me
know
-MORPHEUS

shridhar@mistralsoftware.com wrote:
> Hi, > > we are reading an ADC o/p through FPGA. To remove the DC Offset present > in the ADC input we have a DAC which can remove this DC offset using a > subtractor before the actual analog input (with added DC offset) goes > to ADC. > > Now I want my FPGA to calculate the DC offset from ADC outputs and then > feed this value to DAC input which in turn cancel the DC offset using > subtrator. > > can anybody suggest me how can i implement this in FPGA? I just gone > through net and realized that i can use a subtractor and a MAC. The ADC > output will go to this Subtractor which has the final output of MAC as > other input. the subtractor output will be multiplied with some small > value K (??) and then an accumulator. The final output of accumulator > can be feedback to the DAC. The DAC o/p is going to Mixer to cancel the > DC offset? > > this is what i understood. can somebody through some light? > > suggestions are welcome. >
You can avoid potential stability issues (can happen with IIR smoothing filters and due to pipeline delays in converters) if you can ensure your ADC inputs are grounded briefly (at startup, or by issuing a "calibrate" command) and measuring the offset. This can be fed back until the offset is below 1 bit. This of course only works if it's the ADC offset you wish to cancel, and not the offset present in the input signal itself -Jim if you are blr based, I used to work in the offices just above yours...