Xilinx Virtex 4 device technology

Does anybody happen to know the if Xilinx Virex 4 and/or the QPRO
familiy of devices are fabricated using the fully depleted SOI (FD SOI)
technology as opposed to the traditional bulk CMOS?

Thanks,

Amr Ahmadain

Amora,

We do not use SOI in any of our products.

Austin

Amora wrote:

> Does anybody happen to know the if Xilinx Virex 4 and/or the QPRO
> familiy of devices are fabricated using the fully depleted SOI (FD SOI)
> technology as opposed to the traditional bulk CMOS?
> 
> Thanks,
> 
> Amr Ahmadain
> 

Austin,

Thanks for your reply. But does that mean there isn't at least any
consideration to use the SOI technology in the near future in building
your devices? I think they do offer intrinsic performance and low-power
edge compared to bulk CMOS.

Thanks again.!

Amr

Amr, within a company like Xilinx, there are hundreds of ongoing
considerations and investigations and plans about hundreds of
possibilities. This newsgroup is a public forum, and you should not
expect us to describe all our planned and not planned developments.
Austin and I are reasonably candid, but we also have an obligation to
keep future plans under wraps. This is a competitive field...
Peter Alfke

Peter & Austin,

I deeply apologize for not being of aware of these issues. My
intentions were good.

Really sorry.

Amr

Peter and Austin,

Again, please do accept my apologies. I asked this question just out of
curiosity and maybe out of naiveness !!

Amr

Amr, do not feel bad. No need to apoligize. Austin and I are able to
decide what we want to tell the public, and what is better left
un-said.
Keep asking questions, and even complaining (hopefully not too much).
We will answer to the best of our ability, but also in loyalty to our
employer.
Cheers
Peter Alfke

Peter,

Thanks a million for the reply. This is really what I needed to hear
from you.

I can tell you for sure, I'll keep asking scores of questions, but
complaining a little:)

Amr

Amr,

No apology necessary.

Some further notes on SOI (that I can share):

In order to remove or minimize the variation in timing in SOI from the 
floating wells, one needs to add taps.  The addition of the taps to 
every well, results in the area increasing dramatically.  That makes the 
FPGA cost too much, hence the process is not commercially viable.  This 
has been one of the reasons for its non-use.

SOI is also heralded as being more robust for atmospheric neutrons.  But 
it is only twice to five times better than bulk substrates.  A factor of 
two to five is not considered good enough to warrant its use.

SOI also does little to increase the LET for heavy ion strikes, unless 
the design has a lot of taps to collect charge (which adds area again).

Xilinx pioneered a major process development with the introduction of 
triple oxide (now running in two completely different fab lines:  UMC 
and Toshiba).  This allowed us to reduce the leakage current of our 
devices substantially, as well as provide an almost two times better SEU 
  time to upset (over the previous generation technology, or other 90nm 
FPGA competition).

We do consider process techology where it can provide the most benefit. 
  In this case, SOI would increase area, not do anything for leakage, 
and cause all kinds of other problems.  Triple oxide solves a number of 
known problems, by using masks and steps that are standard to the semi 
industry.

Austin

Amr Ahmadain wrote:

> Peter and Austin,
> 
> Again, please do accept my apologies. I asked this question just out of
> curiosity and maybe out of naiveness !!
> 
> Amr
> 

Austin Lesea schrieb:

> In order to remove or minimize the variation in timing in SOI from the
> floating wells, one needs to add taps.  The addition of the taps to
> every well, results in the area increasing dramatically.  That makes the
> FPGA cost too much, hence the process is not commercially viable.  This
> has been one of the reasons for its non-use.

Also, without knowing as much detauls as austin, I suspect that in a
design as heavily dominated by interconnect as an FPGA the area increase
results in longer wires which increases capacitance and therefore power
consumption and delay. This mitigates the two main advantages of SOI.

Kolja Sulimma