Small FPGA

Hello,

I'd like to find a really small FPGA that I could solder by hand,
like in a VQ44 or VQ64 package. Ideally, it should only require a
single 3.3v supply, but a dual supply core/io would be OK too if
really necessary.

I really don't need many logic probably as few as 500 LE.

I tried the XC9500 CPLD line from xilinx but it seems my application
doesn't fit CPLD well, I basically need counters, registers and
mux.


	Sylvain

"Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag
news:42c25994$0$28322$ba620e4c@news.skynet.be...
> Hello,
>
> I'd like to find a really small FPGA that I could solder by hand,
> like in a VQ44 or VQ64 package. Ideally, it should only require a
> single 3.3v supply, but a dual supply core/io would be OK too if
> really necessary.
>
> I really don't need many logic probably as few as 500 LE.
>
> I tried the XC9500 CPLD line from xilinx but it seems my application
> doesn't fit CPLD well, I basically need counters, registers and
> mux.
>
> Sylvain

there unfortunatly arent any FPGAs in VQ44 or VQ64 package :(
the smalles FPGA packages (non BGA) are TQFP100 what is pretty much larger
already.
by had you can actually solder very nicely also QFN packages but there are
virtually no FPGA in QFN at all,

actel A3P030 should be offered in QN132 (I assume its QFN not BGA!), but
ASFAIK it is not available

Atmels FPSLIC is coming to small 8by8 package, but again its not available
and I think its BGA (there is not even info about this)

so everything that has smaller PCB footprint than TQFP100 is already in BGA
or not available

you should try to fit your design into PLD, you have better luck to find
smaller PLD devices, but well sure the PLD prices go up much more faster
when you need more macrocells.

the 'design for fit' for PLDs s totally different from FPGA, so by doing
special optimization for PLD you may fit way more into a PLD then you think

two examples from my experience

1) a complete MMC card controller that support MMC protocol (not SPI) and
loads the all bits from MMC card, it takes 20 PLD macrocells (in coolrunner,
21 in XC9500), that is way less than, well if you think its only 20 flip
flops! this design is specilla optimized for PLD

2) recently I was asked to display a textual message on intelligent display,
using a PLD, well the PLD was already full having a macrocells free, but to
my own surprise the display of an text string involved only an addition of 1
flip flop, well this one flip re-targetted most of the existing macrocells
to have secondary function...

counters and muxes and registers are quite easy in PLD, but the amount of
registers is sure limited, all flip flops have a way higher 'price' than the
flipp flops in FPGA

hm, the larger PLD are also in packages larger than VQ64 :( so there isnt
much that fits your requirements

I would go with MAX2 in TQFP100, but if that package is too large than you
have to wait for APA030 QN132, or maybe there is something else coming out
sooner, lattice promised some new PLD devices to be announced 'after your
summer vaccation'

Antti

Hi Antti

> you should try to fit your design into PLD, you have better luck to find
> smaller PLD devices, but well sure the PLD prices go up much more faster
> when you need more macrocells.
> 
> the 'design for fit' for PLDs s totally different from FPGA, so by doing
> special optimization for PLD you may fit way more into a PLD then you think

Yes, indeed my "style" is more based on FPGA experience.
What would be the "CPLD" way to code a debouncer ?


> I would go with MAX2 in TQFP100, but if that package is too large than you
> have to wait for APA030 QN132, or maybe there is something else coming out
> sooner, lattice promised some new PLD devices to be announced 'after your
> summer vaccation'

I'm kind of in a hurry ;)


Thanks for the insight,


	Sylvain

"Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag
news:42c27017$0$23344$ba620e4c@news.skynet.be...
> Hi Antti
>
> > you should try to fit your design into PLD, you have better luck to find
> > smaller PLD devices, but well sure the PLD prices go up much more faster
> > when you need more macrocells.
> >
> > the 'design for fit' for PLDs s totally different from FPGA, so by doing
> > special optimization for PLD you may fit way more into a PLD then you
think
>
> Yes, indeed my "style" is more based on FPGA experience.
> What would be the "CPLD" way to code a debouncer ?

not everything can be pld optimized. if you only have 100mhz clock and need
some low frequency then you need some amount of flip flops to implement the
counter.

so if you need to debounce a mechanical switch you might need lots of flip
flops (assuming only high frequency clock is available) - a 'saving' in PLD
would be to have separate RC oscillator to get low frequency needed for
debounce

the most savings in PLD come from resources sharing, as example if you have
a need a counter and and shift register, but they are never active at same
time, you can use the same macrocells, that is 8 bit counter and 8 bit shift
register consumes 8 PLD macrocells (but they are not useable at the same
time).

the 500LE (if that is LE as in Altera) would defenetly fit into a PLD but
the LE to PLD macrocell ratio depends on the application, if there is really
lots of (wide) logic, 500LEs could be even as small as 72 PLD macrocells (eg
fit XC9572 VQ64), if the design is register rich then the ratio would be 1:1

note that altera MAX2 is not a PLD, but simplified FPGA, so the LE to MAX2
cell is 1:1 there is no reduction

 > > I would go with MAX2 in TQFP100, but if that package is too large than
you
> > have to wait for APA030 QN132, or maybe there is something else coming
out
> > sooner, lattice promised some new PLD devices to be announced 'after
your
> > summer vaccation'
>
> I'm kind of in a hurry ;)
>
>
> Thanks for the insight,
>
>
> Sylvain

if in hurry then you must either use TQFP100 package or BGA

Antti

Hi Antti,

> 
> 
> if in hurry then you must either use TQFP100 package or BGA


Finally I think I wont use PLD at all.
A RC filter for "quick & dirty" pre-debounce and a simple 8bit �C
to handle to rest of the logic will do. It doesn't need to be very
fast anyway.


	Sylvain

"Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag
news:42c27a2c$0$29635$ba620e4c@news.skynet.be...
>
> Hi Antti,
>
> >
> >
> > if in hurry then you must either use TQFP100 package or BGA
>
>
> Finally I think I wont use PLD at all.
> A RC filter for "quick & dirty" pre-debounce and a simple 8bit &#4294967295;C
> to handle to rest of the logic will do. It doesn't need to be very
> fast anyway.
>
>
> Sylvain

HAHA, that is good optimization!!!! from 500LE down to 0!
with proper firmware you may not need the external debounce but it all
depends sometime the rc network is good choice

sure if there is no direct need for high speed logic then small flash micro
is better choice.

my current favorite is ATmega8 in QFN32 package, but thats all a matter of
taste

Antti

"Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag
news:42c27017$0$23344$ba620e4c@news.skynet.be...

> Yes, indeed my "style" is more based on FPGA experience.
> What would be the "CPLD" way to code a debouncer ?

A counter and some logic will do. CPLD or FPGA doesnt matter here.

Regarads
Falk

Falk Brunner wrote:
> "Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag
> news:42c27017$0$23344$ba620e4c@news.skynet.be...
> 
> 
>>Yes, indeed my "style" is more based on FPGA experience.
>>What would be the "CPLD" way to code a debouncer ?
> 
> 
> A counter and some logic will do. CPLD or FPGA doesnt matter here.
> 
> Regarads
> Falk

The problem is that I need 8 of them + some other stuff,
the debouncers fits but uses most of the 72 macrocells and the price
goes high quickly for more macrocells.


	Sylvain

"Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag
news:42c2cdce$0$337$ba620e4c@news.skynet.be...

> The problem is that I need 8 of them + some other stuff,
> the debouncers fits but uses most of the 72 macrocells and the price
> goes high quickly for more macrocells.

I assume the debouncers are for push buttons? This can be easyly handled in
a microcontroller. And this is also very cheap.

Regards
Falk

Sylvain Munaut wrote:
> Falk Brunner wrote:
> 
>>"Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag
>>news:42c27017$0$23344$ba620e4c@news.skynet.be...
>>
>>
>>
>>>Yes, indeed my "style" is more based on FPGA experience.
>>>What would be the "CPLD" way to code a debouncer ?
>>
>>
>>A counter and some logic will do. CPLD or FPGA doesnt matter here.
>>
>>Regarads
>>Falk
> 
> 
> The problem is that I need 8 of them + some other stuff,
> the debouncers fits but uses most of the 72 macrocells and the price
> goes high quickly for more macrocells.

Then use less :)
A debounce really just needs to remove the unwanted edges, so
you do not need many macrocells/key.
ie Slower clock, and fewer MC is another way.
-jg