QII simulation annoyance

tns wrote:
> Mike Treseler wrote:
>
> > tns1 wrote:
> >
> >> Many of the nodes I want to probe seem unavailable in the simulation.
> >> They are either optimized away, or refuse to show up in the simulation
> >> window even when selected in the vwf.
> >
> >
> > For complex designs, it is common practice
> > to write HDL source and simulate *that* using
> > a vhdl simulator, before running Quartus.
> >
> >        -- Mike Treseler
>
> Sounds like a good thing to do. Which tools provide this 'source level'
> simulation? Any free ones?

You should be able to download a free version of ModelSim from Altera's
web site.

-a

tns1 wrote:
> GMM50 wrote:
>
> > The approach I've taken is to add pins to get the desired signals to
> > appear as module ports.  This works great if I'm simulating sub sets of
> > the final design.   And in the total design these pins will eventually
> > get optomized away.
> >
> > If you get to the top level and need to see pins then you need to get
> > then to output pins on the device.  If you're out of pins I put them
> > into a mux and this will keep the signals available for viewing.
> >
> > This all works great for functional simulatins.
> >
> > Good Luck.
> > george
> >
> OK, but what about when the signal looks OK in the sim, but it does not
> appear on the chip?

Maybe it got optimized away for a reason?

-a

Andy Peters wrote:
> tns1 wrote:
> 
>>GMM50 wrote:
>>
>>
>>>The approach I've taken is to add pins to get the desired signals to
>>>appear as module ports.  This works great if I'm simulating sub sets of
>>>the final design.   And in the total design these pins will eventually
>>>get optomized away.
>>>
>>>If you get to the top level and need to see pins then you need to get
>>>then to output pins on the device.  If you're out of pins I put them
>>>into a mux and this will keep the signals available for viewing.
>>>
>>>This all works great for functional simulatins.
>>>
>>>Good Luck.
>>>george
>>>
>>
>>OK, but what about when the signal looks OK in the sim, but it does not
>>appear on the chip?
> 
> 
> Maybe it got optimized away for a reason?
> 
> -a
Maybe so, but why does the sim say otherwise? I thought the whole point of
doing a timing simulation was to know exactly how it would behave. Of 
course my test vectors might not reflect real life.

Can you clarify what is happening?

Are you saying that when you simulate a subdesign, or the whole design, all 
its outputs look OK, but when you run the entire design in hardware it 
doesn't work?  Or are you saying that when you simulate the whole design the 
simulation does not pass, even though the components worked?

The likely problems are different in those two cases.

Vaughn
Altera
[v b e t z (at) altera.com]

"tns" <tns1@cox.net> wrote in message news:de3Be.8730$Eo.918@fed1read04...
> This is useful, but not what I need right now. I am now faced with the 
> problem of having a good timing sim, but a non-functioning design. 
> Essential signals that appear OK in the sub-project sim are being removed 
> somehow when I compile the whole project. What would cause the sim results 
> to be incorrect?
>
> I have a verilog top module which contains both verilog and vhdl modules. 
> Is there some strange rule about connecting ports when mixing language 
> modules? I am only having problems with the vhdl outputs.
>
>
>
> Vaughn Betz wrote:
>
>> See http://www.altera.com/support/kdb/2003/05/rd05142003_7103.html
>>
>> It describes how to use the "keep" attribute to preserve a combinational 
>> node, and the "preserve" attribute to preserve a register.  If you set 
>> the appropriate attribute on a node, it will prevent the optimization 
>> algorithms from removing it, even if that would result in a more 
>> efficient circuit. Hence you can select and view it in a simulator after 
>> compilation (either functional or timing simulation).  As some other 
>> posters have pointed out, you can also bring the signal out to a pin, 
>> which is an indirect way of forcing it to be preserved -- this is often 
>> less convenient in a large design, however.
>>
>> See the Quartus online help for examples of the precise syntax to use to 
>> set these attributes.
>>
>> Regards,
>>
>> Vaughn
>> Altera
>> [v b e t z (at) altera.com]
>>
>> "tns1" <tns1@cox.net> wrote in message 
>> news:wWEAe.8412$Eo.7045@fed1read04...
>>
>>>Many of the nodes I want to probe seem unavailable in the simulation. 
>>>They are either optimized away, or refuse to show up in the simulation 
>>>window even when selected in the vwf.
>>>
>>>Is there a way to prevent this from happening such as a setting an 
>>>optimization level or marking registers so they will be available?
>>>
>>>thanks
>>>
>>
>>
>>
>