Does the Zynq7000 family contain any stored charge circuitry on the chip? The manual says there is "On-chip boot ROM", but is it mask-programmed or flash? If there are flash cells, then what other SRAM-only ARM+FPGA chips should I look at? Best regards, Piotr
Is Zynq7000 leaky?
Started by ●February 18, 2018
Reply by ●February 18, 20182018-02-18
On 2/18/18 7:35 AM, Piotr Wyderski wrote:> Does the Zynq7000 family contain any stored charge circuitry on > the chip? The manual says there is "On-chip boot ROM", but is > it mask-programmed or flash? If there are flash cells, then what > other SRAM-only ARM+FPGA chips should I look at? > > Best regards, PiotrMy memory of the part was that boot code mentioned is mask rom configured by Xilinx, which is run automatically on power on, and that boot loader determines the requested First Level Boot device, loads the program from it into the built in SRam, and executes it. I thought I remembered that the only flash cells was a very small block to configure the 'Secure Boot' mode, and to store the encryption key for secure boot.
Reply by ●February 18, 20182018-02-18
Den søndag den 18. februar 2018 kl. 19.48.50 UTC+1 skrev Richard Damon:> On 2/18/18 7:35 AM, Piotr Wyderski wrote: > > Does the Zynq7000 family contain any stored charge circuitry on > > the chip? The manual says there is "On-chip boot ROM", but is > > it mask-programmed or flash? If there are flash cells, then what > > other SRAM-only ARM+FPGA chips should I look at? > > > > Best regards, Piotr > > My memory of the part was that boot code mentioned is mask rom > configured by Xilinx, which is run automatically on power on, and that > boot loader determines the requested First Level Boot device, loads the > program from it into the built in SRam, and executes it. > > I thought I remembered that the only flash cells was a very small block > to configure the 'Secure Boot' mode, and to store the encryption key for > secure boot.that is efuses, one time programmable
Reply by ●February 18, 20182018-02-18
lasselangwadtchristensen@gmail.com wrote:>> My memory of the part was that boot code mentioned is mask rom >> configured by Xilinx, which is run automatically on power on, and that >> boot loader determines the requested First Level Boot device, loads the >> program from it into the built in SRam, and executes it. >> >> I thought I remembered that the only flash cells was a very small block >> to configure the 'Secure Boot' mode, and to store the encryption key for >> secure boot. > > that is efuses, one time programmableGents, that sounds nice, thanks. So I have a follow-up question: is it possible to force Zynq to use single DOUT SPI configuration? The manual says the chip supports QSPI and requires four DOUT wires, but QSPI starts in 1x mode by default, so I am confused. The reason is that I would like to configure the chip from a voting memory module in order to avoid configuration stream (and other persistent data) corruption and provide one memory chip failure tolerance. The x4 mode would imply fourfold replication of the voting circuitry and the bidirectional nature of DIN doesn't help either. The old good SPI protocol could be nicely covered by a single 74AC251 8:1 MUX. Best regards, Piotr
Reply by ●February 18, 20182018-02-18
On 2/18/18 2:20 PM, lasselangwadtchristensen@gmail.com wrote:> Den søndag den 18. februar 2018 kl. 19.48.50 UTC+1 skrev Richard Damon: >> On 2/18/18 7:35 AM, Piotr Wyderski wrote: >>> Does the Zynq7000 family contain any stored charge circuitry on >>> the chip? The manual says there is "On-chip boot ROM", but is >>> it mask-programmed or flash? If there are flash cells, then what >>> other SRAM-only ARM+FPGA chips should I look at? >>> >>> Best regards, Piotr >> >> My memory of the part was that boot code mentioned is mask rom >> configured by Xilinx, which is run automatically on power on, and that >> boot loader determines the requested First Level Boot device, loads the >> program from it into the built in SRam, and executes it. >> >> I thought I remembered that the only flash cells was a very small block >> to configure the 'Secure Boot' mode, and to store the encryption key for >> secure boot. > > that is efuses, one time programmable >Yes, likely efuses as not erasable. I do remember the comments about practicing your encription procedures using battery backed up alternate key storage to avoid making bricks. Not having any flash cells would simplify the process.
Reply by ●February 18, 20182018-02-18
On 2/18/18 3:01 PM, Piotr Wyderski wrote:> lasselangwadtchristensen@gmail.com wrote: > >>> My memory of the part was that boot code mentioned is mask rom >>> configured by Xilinx, which is run automatically on power on, and that >>> boot loader determines the requested First Level Boot device, loads the >>> program from it into the built in SRam, and executes it. >>> >>> I thought I remembered that the only flash cells was a very small block >>> to configure the 'Secure Boot' mode, and to store the encryption key for >>> secure boot. >> >> that is efuses, one time programmable > > Gents, that sounds nice, thanks. So I have a follow-up question: > is it possible to force Zynq to use single DOUT SPI configuration? > The manual says the chip supports QSPI and requires four DOUT wires, > but QSPI starts in 1x mode by default, so I am confused. > > The reason is that I would like to configure the chip from > a voting memory module in order to avoid configuration stream > (and other persistent data) corruption and provide one memory > chip failure tolerance. The x4 mode would imply fourfold > replication of the voting circuitry and the bidirectional > nature of DIN doesn't help either. The old good SPI protocol > could be nicely covered by a single 74AC251 8:1 MUX. > > Best regards, PiotrMy guess you would need to put that question to Xilinx Tech Support. The mask programmed boot loader may (likely) not have code to handle that sort of case.
Reply by ●February 18, 20182018-02-18
Richard Damon wrote:> My guess you would need to put that question to Xilinx Tech Support. The > mask programmed boot loader may (likely) not have code to handle that > sort of case.IMHO it would be enough to prevent it bumping the interface speed to x4. Since it must start in x1 mode, the mode must certainly be supported. Best regards, Piotr
Reply by ●February 18, 20182018-02-18
Den søndag den 18. februar 2018 kl. 21.01.22 UTC+1 skrev Piotr Wyderski:> lasselangwadtchristensen@gmail.com wrote: > > >> My memory of the part was that boot code mentioned is mask rom > >> configured by Xilinx, which is run automatically on power on, and that > >> boot loader determines the requested First Level Boot device, loads the > >> program from it into the built in SRam, and executes it. > >> > >> I thought I remembered that the only flash cells was a very small block > >> to configure the 'Secure Boot' mode, and to store the encryption key for > >> secure boot. > > > > that is efuses, one time programmable > > Gents, that sounds nice, thanks. So I have a follow-up question: > is it possible to force Zynq to use single DOUT SPI configuration? > The manual says the chip supports QSPI and requires four DOUT wires, > but QSPI starts in 1x mode by default, so I am confused. > > The reason is that I would like to configure the chip from > a voting memory module in order to avoid configuration stream > (and other persistent data) corruption and provide one memory > chip failure tolerance. The x4 mode would imply fourfold > replication of the voting circuitry and the bidirectional > nature of DIN doesn't help either. The old good SPI protocol > could be nicely covered by a single 74AC251 8:1 MUX. > > Best regards, Piotrhttps://forums.xilinx.com/t5/Embedded-Processor-System-Design/Zynq-QPSI-Boot-from-Legacy-1-Bit-SPI-Device/td-p/383065
Reply by ●February 18, 20182018-02-18
On 2/18/18 3:42 PM, Piotr Wyderski wrote:> Richard Damon wrote: > >> My guess you would need to put that question to Xilinx Tech Support. >> The mask programmed boot loader may (likely) not have code to handle >> that sort of case. > > IMHO it would be enough to prevent it bumping the interface speed to x4. > Since it must start in x1 mode, the mode must certainly be supported. > > Best regards, PiotrBut the Mask Programmed Boot Code may just hard wire send the command to shift to x4 mode, and then run assuming x4 mode. The support hardware list only list Quad-SPI parts (and not even all of them), so their design space may have been limited. That is why I suggest contacting Tech Support. We can just guess, they can look at the internals of the design and possibly know (or possibly just say it isn't documented, so it isn't available).
Reply by ●February 19, 20182018-02-19
On 2018-02-18 lasselangwadtchristensen@gmail.com wrote in comp.arch.fpga:> Den søndag den 18. februar 2018 kl. 21.01.22 UTC+1 skrev Piotr Wyderski: >> lasselangwadtchristensen@gmail.com wrote: >> >> >> My memory of the part was that boot code mentioned is mask rom >> >> configured by Xilinx, which is run automatically on power on, and that >> >> boot loader determines the requested First Level Boot device, loads the >> >> program from it into the built in SRam, and executes it. >> >> >> >> I thought I remembered that the only flash cells was a very small block >> >> to configure the 'Secure Boot' mode, and to store the encryption key for >> >> secure boot. >> > >> > that is efuses, one time programmable >> >> Gents, that sounds nice, thanks. So I have a follow-up question: >> is it possible to force Zynq to use single DOUT SPI configuration? >> The manual says the chip supports QSPI and requires four DOUT wires, >> but QSPI starts in 1x mode by default, so I am confused. >> >> The reason is that I would like to configure the chip from >> a voting memory module in order to avoid configuration stream >> (and other persistent data) corruption and provide one memory >> chip failure tolerance. The x4 mode would imply fourfold >> replication of the voting circuitry and the bidirectional >> nature of DIN doesn't help either. The old good SPI protocol >> could be nicely covered by a single 74AC251 8:1 MUX. >> >> Best regards, Piotr > > https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Zynq-QPSI-Boot-from-Legacy-1-Bit-SPI-Device/td-p/383065-- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) You know it's going to be a bad day when you want to put on the clothes you wore home from the party and there aren't any.
