Hi, I'm trying to process a Ethernet type package. Suppose if i have detected SFD and now have a <1600Byte data. I'm extracting different package element(ds_addr,src_addr,etc) concatenating them in a long shift register and at same time passing it to a fifo to buffer and calculating crc32 which will take some clock cycles(xoring and shifting). Now if calculated CRC matched what is received, pass data to nxt stage else rst fifo. Is there a better technique for it? Thank-You in advance.
How to handle a data packet while calculating CRC.
Started by ●March 12, 2018
Reply by ●March 12, 20182018-03-12
On 2018-03-12 12:02, yogesh tripathi wrote:> Hi, > > I'm trying to process a Ethernet type package. Suppose if i have detected SFD and now have a <1600Byte data. > > I'm extracting different package element(ds_addr,src_addr,etc) concatenating them in a long shift register and at same time passing it to a fifo to buffer and calculating crc32 which will take some clock cycles(xoring and shifting). Now if calculated CRC matched what is received, pass data to nxt stage else rst fifo. > > > Is there a better technique for it? > > Thank-You in advance. >Hi Calculate CRC on-the-fly together with incoming data. Adam
Reply by ●March 13, 20182018-03-13
On Monday, March 12, 2018 at 6:22:39 PM UTC+5:30, Adam Górski wrote:> On 2018-03-12 12:02, yogesh tripathi wrote: > > Hi, > > > > I'm trying to process a Ethernet type package. Suppose if i have detected SFD and now have a <1600Byte data. > > > > I'm extracting different package element(ds_addr,src_addr,etc) concatenating them in a long shift register and at same time passing it to a fifo to buffer and calculating crc32 which will take some clock cycles(xoring and shifting). Now if calculated CRC matched what is received, pass data to nxt stage else rst fifo. > > > > > > Is there a better technique for it? > > > > Thank-You in advance. > > > > Hi > > Calculate CRC on-the-fly together with incoming data. > > AdamHi Adam, "Calculate CRC on-the-fly together with incoming data." , can you elaborate it a bit more. I'm getting a 8bit data in one clock cycle from the decoder. Now for crc i need serial shift register.
Reply by ●March 13, 20182018-03-13
Implement this transition function as your 8-bit data is coming in on each cyle: https://en.wikipedia.org/wiki/Cyclic_redundancy_check#CRC-32_algorithm Or you could have a 2x clock for the inner loop to fit the table access, or compute everything one byte per clock cycle by pipelining the accesses such as: crc32_now = crc32_prev[23:0] XOR output_from_sram_one_cycle_delay lookup_sram_index_next = crc32_now[7:0] XOR data_from_packet crc32_prev = crc32_now Then make sure you handle the reset conditions on packet start, end of packet, etc. On Tuesday, March 13, 2018 at 12:05:15 AM UTC-4, yogesh tripathi wrote:> On Monday, March 12, 2018 at 6:22:39 PM UTC+5:30, Adam Górski wrote: > > On 2018-03-12 12:02, yogesh tripathi wrote: > > > Hi, > > > > > > I'm trying to process a Ethernet type package. Suppose if i have detected SFD and now have a <1600Byte data. > > > > > > I'm extracting different package element(ds_addr,src_addr,etc) concatenating them in a long shift register and at same time passing it to a fifo to buffer and calculating crc32 which will take some clock cycles(xoring and shifting). Now if calculated CRC matched what is received, pass data to nxt stage else rst fifo. > > > > > > > > > Is there a better technique for it? > > > > > > Thank-You in advance. > > > > > > > Hi > > > > Calculate CRC on-the-fly together with incoming data. > > > > Adam > > Hi Adam, > > "Calculate CRC on-the-fly together with incoming data." , can you elaborate it a bit more. > I'm getting a 8bit data in one clock cycle from the decoder. Now for crc i need serial shift register.
Reply by ●March 13, 20182018-03-13
On Mon, 12 Mar 2018 21:05:09 -0700 (PDT), yogesh tripathi <yogitripathi47@gmail.com> wrote:> I'm getting a 8bit data in one clock cycle from the decoder. Nowfor crc i => need serial shift register.You have some options: 1. Use a precalculated table (rainbow table) for CRC. With 8 bit the size of the table is usually acceptable. 2. Use the 8x clock for the CRC calculating shift register (not recommended here). 3. Use a pipelined CRC calculation: The calc module is 8 times in parallel and you get the final result with eight clocks latency. Bart
Reply by ●March 13, 20182018-03-13
In article <almarsoft.7981620793307616371@news.eternal-september.org>, Bart Fox <bartfox@gmx.net> wrote:>On Mon, 12 Mar 2018 21:05:09 -0700 (PDT), yogesh tripathi ><yogitripathi47@gmail.com> wrote: >> I'm getting a 8bit data in one clock cycle from the decoder. Now >for crc i = >> need serial shift register. >You have some options: >1. Use a precalculated table (rainbow table) for CRC. With 8 bit the >size of the table is usually acceptable. >2. Use the 8x clock for the CRC calculating shift register (not >recommended here). >3. Use a pipelined CRC calculation: The calc module is 8 times in >parallel and you get the final result with eight clocks latency.Table methods are very likely NOT the correct solution for FPGA implementations. Those methods are tuned for SW solutions. CRCs in hardware are actually quite easy / low resources. Shifting through the 8 bits in one clock cycle will probably work just fine. There's online websites that have "CRC" calculators which can do some of this work for you. But I find just coding up the algorithm in verilog / VHDL to be more compact and clear. If that doesn't work - i.e. you're not hitting you're desired clock frequencies - then Bart's suggestion of pipelining the calc is valid. That can be a little trickier, but still doable. I don't think you'll need to go this far, unless you're trying to hit some high clock rates. Regards, Mark
Reply by ●March 13, 20182018-03-13
On 13/03/2018 04:05, yogesh tripathi wrote:> On Monday, March 12, 2018 at 6:22:39 PM UTC+5:30, Adam Górski wrote: >> On 2018-03-12 12:02, yogesh tripathi wrote: >>> Hi, >>> >>> I'm trying to process a Ethernet type package. Suppose if i have detected SFD and now have a <1600Byte data. >>> >>> I'm extracting different package element(ds_addr,src_addr,etc) concatenating them in a long shift register and at same time passing it to a fifo to buffer and calculating crc32 which will take some clock cycles(xoring and shifting). Now if calculated CRC matched what is received, pass data to nxt stage else rst fifo. >>> >>> >>> Is there a better technique for it? >>> >>> Thank-You in advance. >>> >> >> Hi >> >> Calculate CRC on-the-fly together with incoming data. >> >> Adam > > Hi Adam, > > "Calculate CRC on-the-fly together with incoming data." , can you elaborate it a bit more. > I'm getting a 8bit data in one clock cycle from the decoder. Now for crc i need serial shift register.Not necessarily, have a look at: http://www.easics.com/webtools/crctool I've used this, albeit a few years ago and the website has changed since. If I recall you have to invert and swap the bit order to get the correct CRC. I used a simulator to check the permutations until I got it right. If you have 8bit data you can generate the CRC on the fly at the same rate. -- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.uk
Reply by ●March 15, 20182018-03-15
On Wednesday, March 14, 2018 at 1:18:40 AM UTC+5:30, Mike Perkins wrote:> On 13/03/2018 04:05, yogesh tripathi wrote: > > On Monday, March 12, 2018 at 6:22:39 PM UTC+5:30, Adam Górski wrote: > >> On 2018-03-12 12:02, yogesh tripathi wrote: > >>> Hi, > >>> > >>> I'm trying to process a Ethernet type package. Suppose if i have detected SFD and now have a <1600Byte data. > >>> > >>> I'm extracting different package element(ds_addr,src_addr,etc) concatenating them in a long shift register and at same time passing it to a fifo to buffer and calculating crc32 which will take some clock cycles(xoring and shifting). Now if calculated CRC matched what is received, pass data to nxt stage else rst fifo. > >>> > >>> > >>> Is there a better technique for it? > >>> > >>> Thank-You in advance. > >>> > >> > >> Hi > >> > >> Calculate CRC on-the-fly together with incoming data. > >> > >> Adam > > > > Hi Adam, > > > > "Calculate CRC on-the-fly together with incoming data." , can you elaborate it a bit more. > > I'm getting a 8bit data in one clock cycle from the decoder. Now for crc i need serial shift register. > > Not necessarily, have a look at: > http://www.easics.com/webtools/crctool > > I've used this, albeit a few years ago and the website has changed since. > > If I recall you have to invert and swap the bit order to get the correct > CRC. I used a simulator to check the permutations until I got it right. > > If you have 8bit data you can generate the CRC on the fly at the same rate. > > > -- > Mike Perkins > Video Solutions Ltd > www.videosolutions.ltd.ukThank-You Mike. The link gives a provide a HDL package which is basically a Parallel LFSR. You know any related text how to generate a custom LFSR for these CRC ,just for better understanding.
Reply by ●March 15, 20182018-03-15
>>> Hi, >>> >>> I'm trying to process a Ethernet type package. Suppose if i have detected SFD and now have a <1600Byte data. >>> >>> I'm extracting different package element(ds_addr,src_addr,etc) concatenating them in a long shift register and at same time passing it to a fifo to buffer and calculating crc32 which will take some clock cycles(xoring and shifting). Now if calculated CRC matched what is received, pass data to nxt stage else rst fifo. >>> >>> >>> Is there a better technique for it? >>> >>> Thank-You in advance. >>> >> >> Hi >> >> Calculate CRC on-the-fly together with incoming data. >> >> Adam > > Hi Adam, > > "Calculate CRC on-the-fly together with incoming data." , can you elaborate it a bit more. > I'm getting a 8bit data in one clock cycle from the decoder. Now for crc i need serial shift register. >So look for CRC implementation able to process 8bits ( byte ) in single clock and store data in same time to fifo and to CRC unit. Hint: Online CRC VHDL generator. There is many. Best regards Adam Górski
Reply by ●March 15, 20182018-03-15
On 15/03/2018 11:28, yogesh tripathi wrote:> On Wednesday, March 14, 2018 at 1:18:40 AM UTC+5:30, Mike Perkins > wrote: >> On 13/03/2018 04:05, yogesh tripathi wrote: >>> On Monday, March 12, 2018 at 6:22:39 PM UTC+5:30, Adam Górski >>> wrote: >>>> On 2018-03-12 12:02, yogesh tripathi wrote: >>>>> Hi, >>>>> >>>>> I'm trying to process a Ethernet type package. Suppose if i >>>>> have detected SFD and now have a <1600Byte data. >>>>> >>>>> I'm extracting different package >>>>> element(ds_addr,src_addr,etc) concatenating them in a long >>>>> shift register and at same time passing it to a fifo to >>>>> buffer and calculating crc32 which will take some clock >>>>> cycles(xoring and shifting). Now if calculated CRC matched >>>>> what is received, pass data to nxt stage else rst fifo. >>>>> >>>>> >>>>> Is there a better technique for it? >>>>> >>>>> Thank-You in advance. >>>>> >>>> >>>> Hi >>>> >>>> Calculate CRC on-the-fly together with incoming data. >>>> >>>> Adam >>> >>> Hi Adam, >>> >>> "Calculate CRC on-the-fly together with incoming data." , can you >>> elaborate it a bit more. I'm getting a 8bit data in one clock >>> cycle from the decoder. Now for crc i need serial shift >>> register. >> >> Not necessarily, have a look at: >> http://www.easics.com/webtools/crctool >> >> I've used this, albeit a few years ago and the website has changed >> since. >> >> If I recall you have to invert and swap the bit order to get the >> correct CRC. I used a simulator to check the permutations until I >> got it right. >> >> If you have 8bit data you can generate the CRC on the fly at the >> same rate. >> >> >> -- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.uk > > Thank-You Mike. The link gives a provide a HDL package which is > basically a Parallel LFSR. You know any related text how to generate > a custom LFSR for these CRC ,just for better understanding.I looked into this a long while ago and gave up! A LFSR is a simple concept in it's own right but I didn't have time to decipher a Parallel LFSR. I made the choice of using the result rather than spend time trying to understand something I would only use once in a long while. I'm sure there are proof and theorems on the 'net somewhere! -- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.uk
