Wanted Actel ProAsic RAM VHDL models

Hi,

I've tried inferring RAMs, but it doesn't seem to work well, so I want
to just instantiate the Actel RAM primitives.

Does anyone have a 4kx9 or 512x18 RAM model that uses
instantiated ProAsic RAM primitives?

Thanks,
Scott                      scd -at- teleport -dot- com

Why don't you use ACTGEN? If you have access to Precision then the example 
below will infer a synchronous memory block,

-------------------------------------------------------------------------------
-- Actel Synchronous Memory
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all; -- yes I know, shouldn't use it :-)

entity ssram is
port(
    clk : in std_logic;
    din128 : in std_logic_vector (127 downto 0);
    addr : in std_logic_vector (3 downto 0);
    we : in std_logic;
    dout128 : out std_logic_vector (127 downto 0)
);
end ssram ;


architecture rtl of ssram is

type mem_type is array (15 downto 0) of std_logic_vector(127 downto 0) ;
signal mem : mem_type;

begin

singleport : process (clk)
    begin
        if (clk'event and clk = '1') then
            if (we = '1') then
                mem(conv_integer(addr)) <= din128;
            else
                dout128 <= mem(conv_integer(addr));
            end if ;
    end if;
end process singleport;

end architecture rtl;

Hans.
www.ht-lab.com

"scd" <scd@nospam.com> wrote in message 
news:ugoBe.7896$8f7.6493@newsread1.news.pas.earthlink.net...
> Hi,
>
> I've tried inferring RAMs, but it doesn't seem to work well, so I want
> to just instantiate the Actel RAM primitives.
>
> Does anyone have a 4kx9 or 512x18 RAM model that uses
> instantiated ProAsic RAM primitives?
>
> Thanks,
> Scott                      scd -at- teleport -dot- com
>
>
>