Doubts on Xilinx FPGA

Hello all,
   Is there any way i can initialise values into the Xilinx FPGA FF. I
am working on the Virtex E FPGA. Please tell me how can i achive that
through verilog.
Thank you

Any flip-flop that has an asynchronous reset or preset term
will be initialized automatically when the FPGA is loaded
from the bitstream.  The standard templates for flip-flops
are available in the Language Templates options of ISE.

Menu:
Edit --> Language Templates...

Navigate to:
Verilog --> Synthesis Templates --> Flip Flops --> D Flip Flop with
Asynchronous Reset

This shows the standard template for inferring flip-flops with
initialization.

Note that any flip-flop that doesn't have an async reset term will
default to zero after bitstream load.

vssumesh wrote:
> Hello all,
>    Is there any way i can initialise values into the Xilinx FPGA FF. I
> am working on the Virtex E FPGA. Please tell me how can i achive that
> through verilog.
> Thank you

"vssumesh" <vssumesh_asic@yahoo.com> wrote in message
news:1121347163.078059.224600@f14g2000cwb.googlegroups.com...
> Hello all,
>    Is there any way i can initialise values into the Xilinx FPGA FF. I
> am working on the Virtex E FPGA. Please tell me how can i achive that
> through verilog.
> Thank you

Aside from the asynchronous clear or preset, some synthesizers will accept
register initialization such as:

reg [7:0] count = 8'h1c;
always @( posedge clk )
  count <= count + 8'h1;

Other synthesizers aren't as good and can apply the xilinx INIT=S or INIT=R
attribute (but it applies to all registers in a vector).
In Synplify, I've been pleading for the former but am using the latter,
typically with macros to make things look cleaner.

`define Init_Hi /* synthesis xc_props="INIT=S" */
reg [7:0] startFromNeg1 `Init_Hi;
always @( posedge clk )
  startFromNeg1 <= startFromNeg1 + 8'h1;

What will be the status of F/F and internal block RAMs of VirtexE FPGA
if i do not specify any initial condition. Can i assume that it is zero
?

What will be the conditions of the F/F and internal block RAM if i
didnt specified any initial value. Can i assume that its zero ??

Internal BlockRAMs will initialize to zero unless you specify other values.
Some BlockRAM outputs (but not on Virtex-E) have an initial state for the
synchronous output specifiable.

The initial state of the registers is a little less obvious.
If a register is preset without a clear or set without a reset (using the
S/R input) the register will initialize high.
If a register isn't preset or set, it will initialize low.  This includes
registers that are reset, cleared, or have no S/R control.

I use the terms "preset" and "clear" for asynchronous events and "set" and
"reset" for synchronous.


"vssumesh" <vssumesh_asic@yahoo.com> wrote in message
news:1121435487.213730.287320@z14g2000cwz.googlegroups.com...
> What will be the status of F/F and internal block RAMs of VirtexE FPGA
> if i do not specify any initial condition. Can i assume that it is zero
> ?

Dear john...
Please tell me the reset condition of internal counters. Is there any
way to initialize the counter also with preset values.

"Dear john"  ...my oh my.

Counters are registers.
1) You can always use the INIT=S and INIT=R attributes on the individual
bits of the counter word in your ucf file.
2) If you're using XST, you might be able to use the initial definition
  reg [7:0] counter = 7'ha5;  // to initialize to hex value a5
3) If you're using Synplify, see 1).
4) If you're using something else I can't help you any further.


"vssumesh" <vssumesh_asic@yahoo.com> wrote in message
news:1121499199.346589.76710@o13g2000cwo.googlegroups.com...
> Dear john...
> Please tell me the reset condition of internal counters. Is there any
> way to initialize the counter also with preset values.

vssumesh wrote:
> Hello all,
>    Is there any way i can initialise values into the Xilinx FPGA FF. I
> am working on the Virtex E FPGA. Please tell me how can i achive that
> through verilog.

Ummmm, how about this simplest, and most portable way?

    always @(posedge clk or negedge rst_l) begin : FlopWithInit
        if (~rst_l) begin
            q <= '1'; -- if you want to preset the flop
        end else begin
            q <= d;
        end
    end // block FlopWithInit

or, if you want to initialize a register to some constant you've
defined:

    parameter INITVAL = 16'hDEAD;

    always @(posedge clk or negedge rst_l) begin : FlopsWithInit
        if (~rst_l) begin
            qq <= INITVAL;
        end else begin
            qq <= dd;
        end
    end // block FlopsWithInit

The trick is that you need a reset signal, but helpful the FPGA
families have power-on global resets that are asserted as part of the
configuration process.

-a

Andy Peters wrote:

> The trick is that you need a reset signal, but helpful the FPGA
> families have power-on global resets that are asserted as part of the
> configuration process.
>
> -a

You don't really need a reset signal, just a reset process.  The
flip-flop you designed could be instantiated with rst_l tied high
at a higher level of hierarchy, but the initialization value after
download would still match the value from the reset process.