Hi, We will soon be using the Nios II as embedded controller and we would like to add a High Speed (HS) USB 2.0 hosting feature that is capable or providing a sustained transfer rate of 20 MBytes/sec. to an external HS USB 2.0 device. I realize that there are a limited number of HS USB 2.0 hosts devices/IP cores currently available. The Phillips ISP1761 is the only HS USB 2.0 component I was able to locate so far and it's not clear to me if this part is readily available. Also, the FPGA-based HS USB 2.0 host IP cores look like they are just now becoming available (www.asics.ws) but they may be cost-prohibitive. Can anyone share their experiences in implementing either a HS USB 2.0 or Full Speed (FS) USB 1.1 host? Is a sustained transfer speed of 20 MBytes/sec. achievable with the assumptions that there are no major transfer bottlenecks in the HS USB 2.0 host component or the associated HS USB 2.0 device (e.g. USB Hard Disk). If not, what is a more reasonable transfer speed goal that has a high probability of success? The choice of which OS with Nios II (or no OS at all) may also be influenced by the max. sustained HS USB 2.0 transfer speed that can be achieved. However, it's also possible that in order to meet the 20 MBytes/sec. goal, the Nios II will have to be "removed" from the data I/O path so that custom FPGA circuitry can handle the transfers directly with the external HS USB 2.0 host transceiver or the IP core. Any information and/or opinions would be helpful. Sincerely, Brad.
NIOS II + USB 2.0 host
Started by ●July 15, 2005
Reply by ●July 15, 20052005-07-15
<bjskill@rocketmail.com> schrieb im Newsbeitrag news:1121398768.643168.106640@o13g2000cwo.googlegroups.com...> Hi, > > We will soon be using the Nios II as embedded controller and we would > like to add a High Speed (HS) USB 2.0 hosting feature that is capable > or providing a sustained transfer rate of 20 MBytes/sec. to an external > HS USB 2.0 device. > > I realize that there are a limited number of HS USB 2.0 hosts > devices/IP cores currently available. The Phillips ISP1761 is the only > HS USB 2.0 component I was able to locate so far and it's not clear to > me if this part is readily available. Also, the FPGA-based HS USB 2.0 > host IP cores look like they are just now becoming available > (www.asics.ws) but they may be cost-prohibitive. > > Can anyone share their experiences in implementing either a HS USB 2.0 > or Full Speed (FS) USB 1.1 host? Is a sustained transfer speed of 20 > MBytes/sec. achievable with the assumptions that there are no major > transfer bottlenecks in the HS USB 2.0 host component or the associated > HS USB 2.0 device (e.g. USB Hard Disk). If not, what is a more > reasonable transfer speed goal that has a high probability of success? > > The choice of which OS with Nios II (or no OS at all) may also be > influenced by the max. sustained HS USB 2.0 transfer speed that can be > achieved. However, it's also possible that in order to meet the 20 > MBytes/sec. goal, the Nios II will have to be "removed" from the data > I/O path so that custom FPGA circuitry can handle the transfers > directly with the external HS USB 2.0 host transceiver or the IP core. > > Any information and/or opinions would be helpful. > > Sincerely, > Brad. >ISP1761 is readily available, the proove is there http://www.hydraxc.com ISP1761 (in BGA) is on lower side of the PCB. non BGA version has been available for some time already, the BGA version (0.5mm pitch!) did become available April/June 2005. and yes, you are about correct for max sustained dataflow the high speed traffic should bypass the processor, that could be done by dedicated DMA and ISP1761 Antti
Reply by ●July 15, 20052005-07-15
Antti, why this is not clearly stated in the datasheet ? To me, it seems a big plus of that little board! Has stack support been implemented on ucLinux ? "Antti Lukats" <antti@openchip.org> ha scritto nel messaggio news:db7i87$92a$01$1@news.t-online.com...> > <bjskill@rocketmail.com> schrieb im Newsbeitrag > news:1121398768.643168.106640@o13g2000cwo.googlegroups.com... >> Hi, >> >> We will soon be using the Nios II as embedded controller and we would >> like to add a High Speed (HS) USB 2.0 hosting feature that is capable >> or providing a sustained transfer rate of 20 MBytes/sec. to an external >> HS USB 2.0 device. >> >> I realize that there are a limited number of HS USB 2.0 hosts >> devices/IP cores currently available. The Phillips ISP1761 is the only >> HS USB 2.0 component I was able to locate so far and it's not clear to >> me if this part is readily available. Also, the FPGA-based HS USB 2.0 >> host IP cores look like they are just now becoming available >> (www.asics.ws) but they may be cost-prohibitive. >> >> Can anyone share their experiences in implementing either a HS USB 2.0 >> or Full Speed (FS) USB 1.1 host? Is a sustained transfer speed of 20 >> MBytes/sec. achievable with the assumptions that there are no major >> transfer bottlenecks in the HS USB 2.0 host component or the associated >> HS USB 2.0 device (e.g. USB Hard Disk). If not, what is a more >> reasonable transfer speed goal that has a high probability of success? >> >> The choice of which OS with Nios II (or no OS at all) may also be >> influenced by the max. sustained HS USB 2.0 transfer speed that can be >> achieved. However, it's also possible that in order to meet the 20 >> MBytes/sec. goal, the Nios II will have to be "removed" from the data >> I/O path so that custom FPGA circuitry can handle the transfers >> directly with the external HS USB 2.0 host transceiver or the IP core. >> >> Any information and/or opinions would be helpful. >> >> Sincerely, >> Brad. >> > > ISP1761 is readily available, the proove is there > http://www.hydraxc.com > > ISP1761 (in BGA) is on lower side of the PCB. non BGA version has been > available for some time already, the BGA version (0.5mm pitch!) did become > available April/June 2005. > > and yes, you are about correct for max sustained dataflow the high speed > traffic should bypass the processor, that could be done by dedicated DMA > and > ISP1761 > > Antti > > > > > > > > > > > > > >
Reply by ●July 15, 20052005-07-15
"Antonio Pasini" <NOSPAM_pasini.a@tin.it> schrieb im Newsbeitrag news:MNSBe.73716$h5.3030923@news3.tin.it...> Antti, > > why this is not clearly stated in the datasheet ? To me, it seems a bigplus> of that little board! > > Has stack support been implemented on ucLinux ? >there is some linux code available for the isp1671 but it has to be adapted and thats not completed. But the goal is to support the isp1671 from uClinux of course Antti> "Antti Lukats" <antti@openchip.org> ha scritto nel messaggio > news:db7i87$92a$01$1@news.t-online.com... > > > > <bjskill@rocketmail.com> schrieb im Newsbeitrag > > news:1121398768.643168.106640@o13g2000cwo.googlegroups.com... > >> Hi, > >> > >> We will soon be using the Nios II as embedded controller and we would > >> like to add a High Speed (HS) USB 2.0 hosting feature that is capable > >> or providing a sustained transfer rate of 20 MBytes/sec. to an external > >> HS USB 2.0 device. > >> > >> I realize that there are a limited number of HS USB 2.0 hosts > >> devices/IP cores currently available. The Phillips ISP1761 is the only > >> HS USB 2.0 component I was able to locate so far and it's not clear to > >> me if this part is readily available. Also, the FPGA-based HS USB 2.0 > >> host IP cores look like they are just now becoming available > >> (www.asics.ws) but they may be cost-prohibitive. > >> > >> Can anyone share their experiences in implementing either a HS USB 2.0 > >> or Full Speed (FS) USB 1.1 host? Is a sustained transfer speed of 20 > >> MBytes/sec. achievable with the assumptions that there are no major > >> transfer bottlenecks in the HS USB 2.0 host component or the associated > >> HS USB 2.0 device (e.g. USB Hard Disk). If not, what is a more > >> reasonable transfer speed goal that has a high probability of success? > >> > >> The choice of which OS with Nios II (or no OS at all) may also be > >> influenced by the max. sustained HS USB 2.0 transfer speed that can be > >> achieved. However, it's also possible that in order to meet the 20 > >> MBytes/sec. goal, the Nios II will have to be "removed" from the data > >> I/O path so that custom FPGA circuitry can handle the transfers > >> directly with the external HS USB 2.0 host transceiver or the IP core. > >> > >> Any information and/or opinions would be helpful. > >> > >> Sincerely, > >> Brad. > >> > > > > ISP1761 is readily available, the proove is there > > http://www.hydraxc.com > > > > ISP1761 (in BGA) is on lower side of the PCB. non BGA version has been > > available for some time already, the BGA version (0.5mm pitch!) didbecome> > available April/June 2005. > > > > and yes, you are about correct for max sustained dataflow the high speed > > traffic should bypass the processor, that could be done by dedicated DMA > > and > > ISP1761 > > > > Antti
Reply by ●July 15, 20052005-07-15
Antti, Thanks for the great feedback. The HydraXC looks like a powerful module that could be incorporated into several types of embedded sytems. Too bad it doesn't incorporate a NIOS II soft-core processor on a Stratix I/II ;-) Other than the indication that the HydraXC has a USB OTG mini-A/B connector, there is nothing else on the datasheet to indicate that this board contains the ISP1761, or any other component(s), that supports HS USB 2.0 hosting. How can you know from the information on the website/datasheet that a USB 2.0 hosting capability if provided? Based on the assumption that a HS USB 2.0 OTG capability is provided, do you know of any HS USB 2.0 transfer speed benchmarks available for the HydraXC using the dedicated DMA channel? I didn't see any benchmark information on their datasheet. I know uClinux for Nios II currently only supports the Full Speed ISP1161A1 and not the ISP1761 components from Philips Do you know which of the listed operating systems that run on the HydraXC support the ISP1761? Since the ISP1761 looks like it is readily available, I start looking into obtaining an evaluation board/kit. Have you done any work with the ISP1761 yourself? The mounting of a 0.5 mm pitch BGA component is non-trivial. We have successfully mounted BGA components with a 0.8 mm pitch so making the jump to a0.5 mm pitch component should be achievable. Brad.
Reply by ●July 17, 20052005-07-17
bjskill@rocketmail.com wrote:> Hi, > > We will soon be using the Nios II as embedded controller and we would > like to add a High Speed (HS) USB 2.0 hosting feature that is capable > or providing a sustained transfer rate of 20 MBytes/sec. to an external > HS USB 2.0 device.Brad, Our USB 2.0 HS host can sustain close to 56Mbytes/sec. Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis ****** Certified USB 2.0 HS OTG and HS Device IP Cores ******> I realize that there are a limited number of HS USB 2.0 hosts > devices/IP cores currently available. The Phillips ISP1761 is the only > HS USB 2.0 component I was able to locate so far and it's not clear to > me if this part is readily available. Also, the FPGA-based HS USB 2.0 > host IP cores look like they are just now becoming available > (www.asics.ws) but they may be cost-prohibitive. > > Can anyone share their experiences in implementing either a HS USB 2.0 > or Full Speed (FS) USB 1.1 host? Is a sustained transfer speed of 20 > MBytes/sec. achievable with the assumptions that there are no major > transfer bottlenecks in the HS USB 2.0 host component or the associated > HS USB 2.0 device (e.g. USB Hard Disk). If not, what is a more > reasonable transfer speed goal that has a high probability of success? > > The choice of which OS with Nios II (or no OS at all) may also be > influenced by the max. sustained HS USB 2.0 transfer speed that can be > achieved. However, it's also possible that in order to meet the 20 > MBytes/sec. goal, the Nios II will have to be "removed" from the data > I/O path so that custom FPGA circuitry can handle the transfers > directly with the external HS USB 2.0 host transceiver or the IP core. > > Any information and/or opinions would be helpful. > > Sincerely, > Brad.
Reply by ●July 17, 20052005-07-17
