DDR SDRAM configuration

Hi,

I have programmed my FPGA with an evaluation bitstream file for
DDR-SDRAM controller.

When measuring bank address bit 0 I can see that
it does not get '1' during initialization phase. That means
that EXTENDED mode register is never written to that is the
DLL is not enabled.

But the evaluation design seems to work.

So how can that be ?

Rgds
Andr=E9