Design is too large for the device! xc3s400

methi wrote:

>Hi Ray,
>
>Are you talking about a BRAM core available in Xilinx?
>
>Ive only come across the RAM based shift reg which goes upto 1024 bits
>(xilinx 6.3i)
>
>Or Should I be working on a BRAM code in vhdl...
>
>
>Thanks,
>
>Methi
>
>  
>
I was talking about a VHDL module with an instantiated RAMB16 primitive 
in it.  Something like this should do the trick for you:

        nxt_addr<= to_unsigned(modulo-2,abits+1) when addr(abits)='1' 
else    addr-1;
        process(clk)
        begin     
                if clk'event and clk='1' then
                    if ce='1' THEN
                        addr<=nxt_addr;
                    end if;       
                end if;
         end process;      
       
        a_addr<=  std_logic_vector(resize(addr(abits-1 downto 0),14))
      
                   U1: ramb16_s1
                --synthesis translate_off 
                generic map(
                    WRITE_MODE_A => "READ_FIRST",
                    WRITE_MODE_B => "READ_FIRST")
                --synthesis translate_on
                port map(
                    DIA  => b_in,
                    ENA  => ce,
                    WEA  => '1',
                    SSRA => '0',
                   CLKA => clk,
                    ADDRA=> a_addr,
                     DOA  =>b_out);       
     
Since your shift register is only 3K+ long, you could even use the other 
RAMB16 port for something else by setting the upper address bits to 
opposite constant values on each port.  The loadable down counter 
reloads when it counts past 0 to -1.  It is coded this way to give the 
synthesis enough of a hint not to stick the load function in as a 
multiplexer after the carry chain, which would force it to two levels of 
logic.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

methi wrote:

> I am just using the output of my shift register...which is the MSB
> (this keeps changing depending on the value of the variable
> "right")...as input to another component....its a pulse...

If you are delaying a single pulse/edge for 3454 ticks,
there are easier ways to do it than with a shift register.

             -- Mike Treseler

Methi,
Take a BlockRAM, with both ports configured as 16K x 1.
Make one port Write and the other one Read. Clock both ports with your
data clock.
Drive the Write address with a counter that you increment with the data
clock.
Drive the Read address from a subtractor circuit that subtracts the
length N of your shift register from the Write address.
Now you have a programmable-length shift register from the D input of
the write port to the Q output of the Read port.
And you get up to 16K bit length in a single BRAM plus four CLBs (14
bit counter plus 14-bit subtractor).
Peter Alfke

Mike Treseler wrote:
> methi wrote:
>
> > I am just using the output of my shift register...which is the MSB
> > (this keeps changing depending on the value of the variable
> > "right")...as input to another component....its a pulse...
>
> If you are delaying a single pulse/edge for 3454 ticks,
> there are easier ways to do it than with a shift register.

Exactly.  He should use a counter that's initialized to required delay
and enabled when he sees his input pulse.  It counts down, and when it
hits zero, an output pulse is generated and the counter is preset back
to his initial value.

There's nothing like getting set on one solution and stubbornly
pursuing it to the point where you're blind to other, simpler,
solutions.

-a

Peter Alfke wrote:

>Methi,
>Take a BlockRAM, with both ports configured as 16K x 1.
>Make one port Write and the other one Read. Clock both ports with your
>data clock.
>Drive the Write address with a counter that you increment with the data
>clock.
>Drive the Read address from a subtractor circuit that subtracts the
>length N of your shift register from the Write address.
>Now you have a programmable-length shift register from the D input of
>the write port to the Q output of the Read port.
>And you get up to 16K bit length in a single BRAM plus four CLBs (14
>bit counter plus 14-bit subtractor).
>Peter Alfke
>
>  
>
Peter, with SPartan3, he can do it with one port of the BRAM if he uses 
a modulo-N count instead of a straight 14 bit binary count.  I showed 
this in the code I posted earlier.  The modulo N count is easy if you do 
it as a loadable down-count that reloads itself when it goes negative.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

Mike Treseler wrote:

> methi wrote:
>
>> I am just using the output of my shift register...which is the MSB
>> (this keeps changing depending on the value of the variable
>> "right")...as input to another component....its a pulse...
>
>
> If you are delaying a single pulse/edge for 3454 ticks,
> there are easier ways to do it than with a shift register.
>
>             -- Mike Treseler

Mike, I assumed this was more like a line buffer where he needed to 
delay a sequence of bits by the 3454 clocks.  If it is indeed just a 
delay from a single pulse and you can guarantee that another pulse does 
not occur until the first one has propagated out, then it can be done 
with just a counter.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

I am trying to delay a pulse by N ticks where N takes a maximum value
of 3454...N is a variable here....

Ray, pretty clever.
But more difficult to understand, or to modify.
And what do I do with the unused port?

But nevertheless, hats off to a smart solution...
Peter

methi schrieb:
> shift_register <= shift_register( 3453 downto 0 ) & shiftin;
This alone would probably synthesize to 256 LUTs configured as SLR16.
No probleme there
> shiftout <= shift_register(right-1);
But this is a 3453 to 1 multiplexer. Without any tricks you need about
2k-LUTs to implement it and it will be reaallllyyyy slow.

So you should use the BRAM as suggested by others.

Kolja Sulimma

methi schrieb:
> I am trying to delay a pulse by N ticks where N takes a maximum value
> of 3454...N is a variable here....

Yes, but a single pulse, or many pulses? That was Rays question.
Can you guarantee that there at most M pulses within 3454 clock cycles?
(with a small value of M)

Kolja Sulimma