The following code: module PROBLEM ( input wire CLK, input wire [9:0] A, input wire [9:0] B, output reg [9:0] OUT ); wire [9:0] xor2; XOR2 XOR2_0 (.O(xor2[0]), .I0(A[0]), .I1(B[0])); XOR2 XOR2_1 (.O(xor2[1]), .I0(A[1]), .I1(B[1])); XOR2 XOR2_2 (.O(xor2[2]), .I0(A[2]), .I1(B[2])); XOR2 XOR2_3 (.O(xor2[3]), .I0(A[3]), .I1(B[3])); XOR2 XOR2_4 (.O(xor2[4]), .I0(A[4]), .I1(B[4])); XOR2 XOR2_5 (.O(xor2[5]), .I0(A[5]), .I1(B[5])); XOR2 XOR2_6 (.O(xor2[6]), .I0(A[6]), .I1(B[6])); XOR2 XOR2_7 (.O(xor2[7]), .I0(A[7]), .I1(B[7])); XOR2 XOR2_8 (.O(xor2[8]), .I0(A[8]), .I1(B[8])); XOR2 XOR2_9 (.O(xor2[9]), .I0(A[9]), .I1(B[9])); always @(posedge CLK) OUT <= xor2; endmodule ... produces interesting results. The tools run without a hitch, no error, and no reports of logic being optimized out. However, if you look at the end-product in the Floorplanner the LUTs that are supposed to be there are nowhere to be found. Then, it gets interesting, go over to FPGA Editor and every bit of logic is there as you would expect. What gives? This excercise started out as an attempt to build an RLOC'd parameterized adder. Logic would not show-up in the Floorplanner so, eventually, I reduced it to just an XOR clocking out to see what was wrong. Using ISE6.1i, SP1. Device is XC2V1000-FG456 ...this is turning out to be one hell of a frustrating week! -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"
Where is the logic?
Started by ●October 9, 2003
Reply by ●October 9, 20032003-10-09
Martin Euredjian wrote:> > The following code: > > module PROBLEM > ( > input wire CLK, > input wire [9:0] A, > input wire [9:0] B, > output reg [9:0] OUT > ); > wire [9:0] xor2; > XOR2 XOR2_0 (.O(xor2[0]), .I0(A[0]), .I1(B[0])); > XOR2 XOR2_1 (.O(xor2[1]), .I0(A[1]), .I1(B[1])); > XOR2 XOR2_2 (.O(xor2[2]), .I0(A[2]), .I1(B[2])); > XOR2 XOR2_3 (.O(xor2[3]), .I0(A[3]), .I1(B[3])); > XOR2 XOR2_4 (.O(xor2[4]), .I0(A[4]), .I1(B[4])); > XOR2 XOR2_5 (.O(xor2[5]), .I0(A[5]), .I1(B[5])); > XOR2 XOR2_6 (.O(xor2[6]), .I0(A[6]), .I1(B[6])); > XOR2 XOR2_7 (.O(xor2[7]), .I0(A[7]), .I1(B[7])); > XOR2 XOR2_8 (.O(xor2[8]), .I0(A[8]), .I1(B[8])); > XOR2 XOR2_9 (.O(xor2[9]), .I0(A[9]), .I1(B[9])); > > always @(posedge CLK) OUT <= xor2; > > endmodule > > ... produces interesting results. The tools run without a hitch, no error, > and no reports of logic being optimized out. However, if you look at the > end-product in the Floorplanner the LUTs that are supposed to be there are > nowhere to be found. Then, it gets interesting, go over to FPGA Editor and > every bit of logic is there as you would expect. What gives? > > This excercise started out as an attempt to build an RLOC'd parameterized > adder. Logic would not show-up in the Floorplanner so, eventually, I > reduced it to just an XOR clocking out to see what was wrong. > > Using ISE6.1i, SP1. Device is XC2V1000-FG456 > > ...this is turning out to be one hell of a frustrating week!You say the LUTs are not there. How about the registers? You might want to open a case for this with Xilinx. It can be an uphill battle trying to get them to understand what you are doing and why. But certainly the problem itself is not difficult to convey. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Reply by ●October 9, 20032003-10-09
"rickman" wrote:> You say the LUTs are not there. How about the registers?Sorry, I should have mentioned that, yes, the registers are there. Floorplanner shows no input to the registers at all, just the output rubberbanding to the corresponding IOB. FPGA Editor shows all logic connected per the HDL description. The bummer here is that I'm trying to create some pretty complex RPM's and Floorplanner is a nice way to see how things are laying out. Unless someone tells me that I'm missing something in my sample code, I guess I'll have to use FPGA Editor.> You might want to open a case for this with Xilinx. It can be an uphill > battle trying to get them to understand what you are doing and why. But > certainly the problem itself is not difficult to convey.They've been pretty good to me in the past...but, then again, I've only put in a couple or so simple cases. I'll typically get myself to the point of absolute frustration before either posting on the newsgroup or seeking other help (like using the Force, which should not be done lightly). :-) -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"
Reply by ●October 9, 20032003-10-09
I wonder if using FMAP might make a difference here? The trouble is... I couldn't figure out how to define a simple two-input XOR gate from both the Libraries Guide and Constraints Guide (MAP) entries. Can anyone point me to detailed documentation on the subject? Thanks, -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:0rahb.13220$BQ7.7883@newssvr25.news.prodigy.com...> The following code: > > module PROBLEM > ( > input wire CLK, > input wire [9:0] A, > input wire [9:0] B, > output reg [9:0] OUT > ); > wire [9:0] xor2; > XOR2 XOR2_0 (.O(xor2[0]), .I0(A[0]), .I1(B[0])); > XOR2 XOR2_1 (.O(xor2[1]), .I0(A[1]), .I1(B[1])); > XOR2 XOR2_2 (.O(xor2[2]), .I0(A[2]), .I1(B[2])); > XOR2 XOR2_3 (.O(xor2[3]), .I0(A[3]), .I1(B[3])); > XOR2 XOR2_4 (.O(xor2[4]), .I0(A[4]), .I1(B[4])); > XOR2 XOR2_5 (.O(xor2[5]), .I0(A[5]), .I1(B[5])); > XOR2 XOR2_6 (.O(xor2[6]), .I0(A[6]), .I1(B[6])); > XOR2 XOR2_7 (.O(xor2[7]), .I0(A[7]), .I1(B[7])); > XOR2 XOR2_8 (.O(xor2[8]), .I0(A[8]), .I1(B[8])); > XOR2 XOR2_9 (.O(xor2[9]), .I0(A[9]), .I1(B[9])); > > always @(posedge CLK) OUT <= xor2; > > endmodule > > > ... produces interesting results. The tools run without a hitch, noerror,> and no reports of logic being optimized out. However, if you look at the > end-product in the Floorplanner the LUTs that are supposed to be there are > nowhere to be found. Then, it gets interesting, go over to FPGA Editorand> every bit of logic is there as you would expect. What gives? > > This excercise started out as an attempt to build an RLOC'd parameterized > adder. Logic would not show-up in the Floorplanner so, eventually, I > reduced it to just an XOR clocking out to see what was wrong. > > Using ISE6.1i, SP1. Device is XC2V1000-FG456 > > ...this is turning out to be one hell of a frustrating week! > > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > > > > > > >
Reply by ●October 9, 20032003-10-09
I haven;t seen this particular problem. There is a problem with the outputs of srl16's not rubberbanding, but the logic is still there. DO you lose the logic in the hierarchical display as well, or is it jsut missing out of the RPM when you try to place it. How about in the placed (grey background) view after you run PAR? Unfortunately, with floorplanner bugs, the best you'll usually get out of Xilinx is an acknowledgement that there is a problem and a promise that it will get addressed in the 'next major release'. Floorplanner still seems to be a very low priority with respect to other parts of the Xilinx tool suite. Martin Euredjian wrote:> "rickman" wrote: > > > You say the LUTs are not there. How about the registers? > > Sorry, I should have mentioned that, yes, the registers are there. > Floorplanner shows no input to the registers at all, just the output > rubberbanding to the corresponding IOB. FPGA Editor shows all logic > connected per the HDL description. > > The bummer here is that I'm trying to create some pretty complex RPM's and > Floorplanner is a nice way to see how things are laying out. Unless someone > tells me that I'm missing something in my sample code, I guess I'll have to > use FPGA Editor. > > > You might want to open a case for this with Xilinx. It can be an uphill > > battle trying to get them to understand what you are doing and why. But > > certainly the problem itself is not difficult to convey. > > They've been pretty good to me in the past...but, then again, I've only put > in a couple or so simple cases. I'll typically get myself to the point of > absolute frustration before either posting on the newsgroup or seeking other > help (like using the Force, which should not be done lightly). :-) > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu"-- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
Reply by ●October 9, 20032003-10-09
Hi Martin, The floorplanner only shows logic that can be floorplanned. The problem is the use of the XOR2 which is a primitive element in the Xilinx Library. This XOR2 element can not be constrained in the UCF file because it is not a LUT it is just logic. If the XOR2 gate was not instantiated then XST would generate a LUT which could be constrained and viewed in the floorplanner. After the map phase it is mapped to a LUT (thus why you see it in the fpga editor), but this is too late to add constraints to. If you add a new definition for the XOR2 to your design, I believe this will fix your problem. You may eventually want to change the name of the XOR2 module in order to avoid confusion with the library primitive. module XOR2 ( output O, input I0, input I1 )/* synthesis attribute lut_map of XOR2 is yes*/; assign O = I0 ^ I1; endmodule // XOR2 - Tom Branca - Xilinx
Reply by ●October 9, 20032003-10-09
The mapped luts will show up in the floorplanner, but not as part of an RPM. If the LUTs get optimized by the mapper, for example if one of the inputs is tied to a constant, the remapped LUT will be put in the primitives bin at the top level of the hierarchy in the floorplanner rather than with the hierarchical component where they originally were unless they are part of an RPM. Run place and route and then open the floorplanner, and look at the placed view. You should see all the logic there. If you then select the luts that are 'dissappearing', then the branch in the hierarchy view will have a box around it and you should be able to push down to find that particular lut. I'm sure you will find it in the primitives bin somewhere, most likely at the top level. If you want it to be part of the RPM you need to either use instantiated luts or FMAP components (which generally get optimized out by synthesis tools). Some synthesis tools, such as synplify have attributes you can put on components to force them into a LUT, and those components will accept an RLOC. When I read your problem statement, I thought you were saying that that logic was not showing up in the floorplanner at all. Tom Branca wrote:> Hi Martin, > The floorplanner only shows logic that can be floorplanned. The > problem is the use of the XOR2 which is a primitive element in the > Xilinx Library. This XOR2 element can not be constrained in the UCF > file because it is not a LUT it is just logic. If the XOR2 gate was > not instantiated then XST would generate a LUT which could be > constrained and viewed in the floorplanner. After the map phase it is > mapped to a LUT (thus why you see it in the fpga editor), but this is > too late to add constraints to. > > If you add a new definition for the XOR2 to your design, I believe > this will fix your problem. You may eventually want to change the name > of the XOR2 module in order to avoid confusion with the library > primitive. > > module XOR2 > ( > output O, > input I0, > input I1 > )/* synthesis attribute lut_map of XOR2 is yes*/; > assign O = I0 ^ I1; > endmodule // XOR2 > > - Tom Branca > - Xilinx-- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
Reply by ●October 9, 20032003-10-09
What tool are you using? Martin Euredjian wrote:> I wonder if using FMAP might make a difference here? The trouble is... I > couldn't figure out how to define a simple two-input XOR gate from both the > Libraries Guide and Constraints Guide (MAP) entries. Can anyone point me to > detailed documentation on the subject? > > Thanks, > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > > "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message > news:0rahb.13220$BQ7.7883@newssvr25.news.prodigy.com... > > The following code: > > > > module PROBLEM > > ( > > input wire CLK, > > input wire [9:0] A, > > input wire [9:0] B, > > output reg [9:0] OUT > > ); > > wire [9:0] xor2; > > XOR2 XOR2_0 (.O(xor2[0]), .I0(A[0]), .I1(B[0])); > > XOR2 XOR2_1 (.O(xor2[1]), .I0(A[1]), .I1(B[1])); > > XOR2 XOR2_2 (.O(xor2[2]), .I0(A[2]), .I1(B[2])); > > XOR2 XOR2_3 (.O(xor2[3]), .I0(A[3]), .I1(B[3])); > > XOR2 XOR2_4 (.O(xor2[4]), .I0(A[4]), .I1(B[4])); > > XOR2 XOR2_5 (.O(xor2[5]), .I0(A[5]), .I1(B[5])); > > XOR2 XOR2_6 (.O(xor2[6]), .I0(A[6]), .I1(B[6])); > > XOR2 XOR2_7 (.O(xor2[7]), .I0(A[7]), .I1(B[7])); > > XOR2 XOR2_8 (.O(xor2[8]), .I0(A[8]), .I1(B[8])); > > XOR2 XOR2_9 (.O(xor2[9]), .I0(A[9]), .I1(B[9])); > > > > always @(posedge CLK) OUT <= xor2; > > > > endmodule > > > > > > ... produces interesting results. The tools run without a hitch, no > error, > > and no reports of logic being optimized out. However, if you look at the > > end-product in the Floorplanner the LUTs that are supposed to be there are > > nowhere to be found. Then, it gets interesting, go over to FPGA Editor > and > > every bit of logic is there as you would expect. What gives? > > > > This excercise started out as an attempt to build an RLOC'd parameterized > > adder. Logic would not show-up in the Floorplanner so, eventually, I > > reduced it to just an XOR clocking out to see what was wrong. > > > > Using ISE6.1i, SP1. Device is XC2V1000-FG456 > > > > ...this is turning out to be one hell of a frustrating week! > > > > > > -- > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > Martin Euredjian > > > > To send private email: > > 0_0_0_0_@pacbell.net > > where > > "0_0_0_0_" = "martineu" > > > > > > > > > > > > > >-- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
Reply by ●October 9, 20032003-10-09
"Ray Andraka" wrote:> What tool are you using?ISE6.1i / XST -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"
Reply by ●October 9, 20032003-10-09
"Ray Andraka" wrote:> When I read your problem statement, I thought you were saying that > that logic was not showing up in the floorplanner at all.That's correct. The LUT's are not showing up at all, anywhere, graphically or otherwise. I just doubled checked that. The Design Hierahchy window shows the IOB's, CLK, DFF's and that's it. Being that it's so short I'll type the contents of the Design Hierarchy window below: PROBLEM "PROBLEM" [31 IOBs, 10 DFFs, 1 BUFG] |_ CLK_BUFGP [BUFGP] O:CLK_BUFGP I:CLK |_ OUT_9 [DFF] Q:OUT_9 D:xor2<9> C:CLK_BUFGP |_ OUT_8 [DFF] Q:OUT_8 D:xor2<8> C:CLK_BUFGP |_ OUT_7 [DFF] Q:OUT_7 D:xor2<7> C:CLK_BUFGP |_ OUT_6 [DFF] Q:OUT_6 D:xor2<6> C:CLK_BUFGP |_ OUT_5 [DFF] Q:OUT_5 D:xor2<5> C:CLK_BUFGP |_ OUT_4 [DFF] Q:OUT_4 D:xor2<4> C:CLK_BUFGP |_ OUT_3 [DFF] Q:OUT_3 D:xor2<3> C:CLK_BUFGP |_ OUT_2 [DFF] Q:OUT_2 D:xor2<2> C:CLK_BUFGP |_ OUT_1 [DFF] Q:OUT_1 D:xor2<1> C:CLK_BUFGP |_ OUT_0 [DFF] Q:OUT_0 D:xor2<0> C:CLK_BUFGP |_ OUT<9> [IOB] O1:xor2<9> OTCLK1:CLK_BUFGP ... weird! |_ OUT<8> [IOB] O1:xor2<8> OTCLK1:CLK_BUFGP ... |_ OUT<7> [IOB] O1:xor2<7> OTCLK1:CLK_BUFGP ... |_ OUT<6> [IOB] O1:xor2<6> OTCLK1:CLK_BUFGP ... |_ OUT<5> [IOB] O1:xor2<5> OTCLK1:CLK_BUFGP ... |_ OUT<4> [IOB] O1:xor2<4> OTCLK1:CLK_BUFGP ... |_ OUT<3> [IOB] O1:xor2<3> OTCLK1:CLK_BUFGP ... |_ OUT<2> [IOB] O1:xor2<2> OTCLK1:CLK_BUFGP ... |_ OUT<1> [IOB] O1:xor2<1> OTCLK1:CLK_BUFGP ... |_ OUT<0> [IOB] O1:xor2<0> OTCLK1:CLK_BUFGP ... |_ CLK [IOB] I:CLK_BUFGP/IBUFG |_ B<9> [IOB]I:B_9_IBUF |_ B<8> [IOB]I:B_8_IBUF |_ B<7> [IOB]I:B_7_IBUF |_ B<6> [IOB]I:B_6_IBUF |_ B<5> [IOB]I:B_5_IBUF |_ B<4> [IOB]I:B_4_IBUF |_ B<3> [IOB]I:B_3_IBUF |_ B<2> [IOB]I:B_2_IBUF |_ B<1> [IOB]I:B_1_IBUF |_ B<0> [IOB]I:B_0_IBUF |_ A<9> [IOB]I:A_9_IBUF |_ A<8> [IOB]I:A_8_IBUF |_ A<7> [IOB]I:A_7_IBUF |_ A<6> [IOB]I:A_6_IBUF |_ A<5> [IOB]I:A_5_IBUF |_ A<4> [IOB]I:A_4_IBUF |_ A<3> [IOB]I:A_3_IBUF |_ A<2> [IOB]I:A_2_IBUF |_ A<1> [IOB]I:A_1_IBUF |_ A<0> [IOB]I:A_0_IBUF This is what's in the FPGA Editor's "List 1" window when set to "All Components": Name Site Type #Pins Hilited A<0> C12 IOB 1 15 A<1> C10 IOB 1 15 A<2> E11 IOB 1 15 A<3> B13 IOB 1 15 A<4> C11 IOB 1 15 A<5> F10 IOB 1 15 A<6> A7 IOB 1 15 A<7> K21 IOB 1 15 A<8> E15 IOB 1 15 A<9> L5 IOB 1 15 B<0> A13 IOB 1 15 B<1> B10 IOB 1 15 B<2> D10 IOB 1 15 B<3> A11 IOB 1 15 B<4> D11 IOB 1 15 B<5> F12 IOB 1 15 B<6> B7 IOB 1 15 B<7> K22 IOB 1 15 B<8> B16 IOB 1 15 B<9> L4 IOB 1 15 CLK D12 IOB 1 15 CLK_BUFGP/BUFG BUFGMUX0S BUFGMUX 3 15 OUT<0> B12 IOB 2 15 OUT<1> F11 IOB 2 15 OUT<2> E12 IOB 2 15 OUT<3> B11 IOB 2 15 OUT<4> F13 IOB 2 15 OUT<5> A10 IOB 2 15 OUT<6> A8 IOB 2 15 OUT<7> K20 IOB 2 15 OUT<8> F14 IOB 2 15 OUT<9> C8 IOB 2 15 PWR_VCC_0 VCC_X19Y1 VCC 1 15 xor2<0> SLICE_X34Y78 SLICE 3 15 xor2<1> SLICE_X26Y79 SLICE 3 15 xor2<2> SLICE_X28Y79 SLICE 3 15 xor2<3> SLICE_X31Y79 SLICE 3 15 xor2<4> SLICE_X30Y78 SLICE 3 15 xor2<5> SLICE_X26Y78 SLICE 3 15 xor2<6> SLICE_X12Y78 SLICE 3 15 xor2<7> SLICE_X62Y46 SLICE 3 15 xor2<8> SLICE_X49Y79 SLICE 3 15 xor2<9> SLICE_X0Y42 SLICE 3 15 Clearly one knows about the LUT's and the other does not. Furthermore, the Floorplanner is showing the outputs coming out of non-existant "xor2" entities. I guess the good news is that the FPGA Editor tells it like it is. (?) -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"
