verilog reg usage

Does <= (reg) changes value at the same clk posedge or the next clk posedge in simulation ? 

On Saturday, 28 April 2018 09:47:42 UTC+8, promach  wrote:
> Does <= (reg) changes value at the same clk posedge or the next clk posedge in simulation ?

all of the usage of non-blocking assignment to a value (the type of it must be 'reg')in always block will lead to the value-changed in the next posedge or negedge of clk.