CPLD 1.8V to 3.3V bidirectional SDA

On Tuesday, May 22, 2018 at 10:26:26 PM UTC-4, Mike Perkins wrote:
> On 21/05/2018 15:19, gnuarm.deletethisbit@gmail.com wrote:
> > On Sunday, May 20, 2018 at 12:21:28 PM UTC-4, Mike Perkins wrote:
> >> On 08/05/2018 15:59, nobody wrote:
> >>> I have a small design flaw with a new sensor, ICM20948, into a PI
> >>> device. I need to make the SDA bidirectional and level shift SCL,
> >>> int, and fsync. Voltage level on the sensor board is 1.8V the PI
> >>> is 3.3V. I have CPLD hardware that I would like to use to make
> >>> the bidirectional level shifted SDA as well as level shift the
> >>> other three.
> >>> 
> >>> The VHDL behavior is as simple as:
> >>> 
> >>> begin
> >>> 
> >>> enable <= '1' when DIR = '1' else '0'; I2C(0) <= SCL; I2C(1) <=
> >>> SDA when enable = '0' else 'Z'; SDA <= I2C(1) when enable = '1'
> >>> else 'Z';
> >>> 
> >>> end Behavioral;
> >>> 
> >>> I have used this before in another I2C without failure. The
> >>> hardware seems to be performing the bidirectional communication,
> >>> but all logic is a ~3.3V level.
> >>> 
> >>> The CPLD is a Xilinx XC2CA64 with the 1.8V I2C pins on 11 and 13
> >>> and the 3.3V I2C and ancillary pins on 15, 16 and 17. The UCF is
> >>> as follows:
> >>> 
> >>> NET "I2C(0)" LOC = "11" ;     #SCL1V8 NET "I2C(0)" IOSTANDARD =
> >>> "LVCMOS18" ; NET "I2C(1)" LOC = "13" ; NET "I2C(1)" IOSTANDARD =
> >>> "LVCMOS18" ; 	#SDA1V8
> >>> 
> >>> NET "SCL"  LOC = "17" ;							#PI side NET "SCL" IOSTANDARD =
> >>> "LVCMOS33" ; 	# NET "SDA"  LOC = "15" ;							#PI side NET "SDA"
> >>> IOSTANDARD = "LVCMOS33" ; 	# NET "DIR"  LOC = "16" ;							#PI
> >>> side NET "DIR" IOSTANDARD = "LVCMOS33" ; 	#
> >> 
> >> Level shifting bidirectional signals is not a trivial thing to do.
> >> 
> >> Agree with Rick's post where the output should either be pulled low
> >> of Hi-Z.
> >> 
> >> What is wrong with the classic way of doing it as per: 
> >> https://www.nxp.com/docs/en/application-note/AN10441.pdf
> >> 
> >> The SCL may also need to be truly bidirectional if there is any
> >> device clock-stretching.
> > 
> > Your point is well taken.  There isn't much chance of clock
> > stretching being used though as some number of I2C masters don't
> > implement it.
> 
> Is it not the slave that holds the clock low, not the master?
>    https://www.i2c-bus.org/clock-stretching/
> 
> Not all devices do this.

Yes, the slave holds the clock low, but the master has to be paying attention.  If not the network screws up. 

Rick C.