Hi Xilinx FPGA's are nice but all of them (after XC4K?) do not have any more access to the OnChipOscillator - it is not usually required also, but in some rare cases it may be useful to have some OnChip Clock available in case all external clock sources fail, or do have emergency Watchdog timer to monitor some events also in the case of external clock circuitry failures. For this purpose we are developing OnChip Oscillator IP Cores. http://gforge.openchip.org/frs/?group_id=32 Simple Spartan-3 version is available, it delivers stable 1:1 duty ratio clock what is in the range of 205-220MHz for S3 -4 speedgrade. Special versions for other Xilinx families are coming shortly. Antti PS to my surprise Lattice EC/XP and also MachXO all have access to their OnChip Oscillator, so at least in thing Xilinx FPGAs have less features available to the user.
OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
Started by ●July 25, 2005
Reply by ●July 25, 20052005-07-25
> > Xilinx FPGA's are nice but all of them (after XC4K?) do not have any more > access to the OnChipOscillator - it is not usually required also, but in > some rare cases it may be useful to have some OnChip Clock available in case > all external clock sources fail, or do have emergency Watchdog timer to > monitor some events also in the case of external clock circuitry failures. > For this purpose we are developing OnChip Oscillator IP Cores. > > http://gforge.openchip.org/frs/?group_id=32 >Just looked at the sources - There are binary VHDL files. What does this mean? Martin
Reply by ●July 25, 20052005-07-25
"Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> schrieb im Newsbeitrag news:42e540a2$0$8024$3b214f66@tunews.univie.ac.at...> > > > Xilinx FPGA's are nice but all of them (after XC4K?) do not have anymore> > access to the OnChipOscillator - it is not usually required also, but in > > some rare cases it may be useful to have some OnChip Clock available incase> > all external clock sources fail, or do have emergency Watchdog timer to > > monitor some events also in the case of external clock circuitryfailures.> > For this purpose we are developing OnChip Oscillator IP Cores. > > > > http://gforge.openchip.org/frs/?group_id=32 > > > Just looked at the sources - There are binary VHDL files. What does > this mean? > > Martin >This means they can only be used by ISE tools. There should be no problems using those files with ISE 6.2 to 7.1, just add to your project and synthesise as normal. If there are any problems let me know. Antti
Reply by ●July 25, 20052005-07-25
Antti Lukats wrote:> "Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> schrieb im Newsbeitrag > news:42e540a2$0$8024$3b214f66@tunews.univie.ac.at... > >>>Xilinx FPGA's are nice but all of them (after XC4K?) do not have any > more >>>access to the OnChipOscillator - it is not usually required also, but in >>>some rare cases it may be useful to have some OnChip Clock available in > case >>>all external clock sources fail, or do have emergency Watchdog timer to >>>monitor some events also in the case of external clock circuitry > failures. >>>For this purpose we are developing OnChip Oscillator IP Cores. >>> >>>http://gforge.openchip.org/frs/?group_id=32Interesting - any data on Vcc and temp variations, and on other frequencies ? Power consumption ? Seems to me, it would be better to create a clock as low as possible, before driving the high-load clock buffers. - thus a cell that is both OSC and Divider could be better ? An advantage of on chip Osc, is they self-margin, so track Vcc and Temp. If I've understood your results, they show quite close correlation across the die. This would also be a good way to see if faster speed grades REALLY are faster, or just stamped to match the market :)>>> >> >>Just looked at the sources - There are binary VHDL files. What does >>this mean? >> >>Martin >> > > This means they can only be used by ISE tools. There should be no problems > using those files with ISE 6.2 to 7.1, just add to your project and > synthesise as normal. If there are any problems let me know.?! - do you mean you cannot save as ASCII source code, or use any other editor ? Surely this nonsense can be disabled ? -jg
Reply by ●July 26, 20052005-07-26
see comments below "Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:42e58544$1@clear.net.nz...> Antti Lukats wrote: > > > "Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> schrieb im Newsbeitrag > > news:42e540a2$0$8024$3b214f66@tunews.univie.ac.at... > > > >>>Xilinx FPGA's are nice but all of them (after XC4K?) do not have any > > more > >>>access to the OnChipOscillator - it is not usually required also, butin> >>>some rare cases it may be useful to have some OnChip Clock available in > > case > >>>all external clock sources fail, or do have emergency Watchdog timer to > >>>monitor some events also in the case of external clock circuitry > > failures. > >>>For this purpose we are developing OnChip Oscillator IP Cores. > >>> > >>>http://gforge.openchip.org/frs/?group_id=32 > > Interesting - any data on Vcc and temp variations, and on other > frequencies ?the OnChip Oscillator is part of larger project and yes we do some measurements, the vcc-temp variatans measurements are not done yet. I only have measured some 5% frequency change in V4 when the chips temp raises from ambient to normal working temp. But the maximal variation can actually be indirectly be calculated from Xilinx datasheets, from my estimate the frwquency should not be off more than +-20% over full temp and vcc range or xilinx datasheet values would not much - that comes from the margin in timing specs in datasheets. of course this applies for one given device-speed grade combination and should be measured in the same CLB location> Power consumption ? > Seems to me, it would be better to create a clock as low as possible, > before driving the high-load clock buffers. - thus a cell that is > both OSC and Divider could be better ? >This cell is OSC and Divider by 2, the high speed signal path (about 440MHz) is kept completly inside the routing switch of an single CLB, ie it is not driving any short or long connections at all, only goes to swithcbox and back. The only load on this net is Divide by stage, what is the actual output of the OCO Cell. we are developing OCO cells with low clock output as well, more suitable for things like watchdog, etc..> An advantage of on chip Osc, is they self-margin, so track Vcc and Temp. > If I've understood your results, they show quite close correlation > across the die. >you understand correctly, the frequencies shown in the screenshot are from different CLB locations accross the die, and the correlation is about what was to be expected.> This would also be a good way to see if faster speed grades REALLY are > faster, or just stamped to match the market :) >Yes, you are a mindreader - this is part of FPGA fine tuning project exactly targetted for timinig measurements of the FPGA internals.> > >>> > >> > >>Just looked at the sources - There are binary VHDL files. What does > >>this mean? > >> > >>Martin > >> > > > > This means they can only be used by ISE tools. There should be noproblems> > using those files with ISE 6.2 to 7.1, just add to your project and > > synthesise as normal. If there are any problems let me know. > > ?! - do you mean you cannot save as ASCII source code, or use any other > editor ? > Surely this nonsense can be disabled ? > > -jg >Sure, ask for commercial licensing and you will get readable source code instantly. At the moment the sources are encrypted to prevent modification. Antti
Reply by ●July 26, 20052005-07-26
Antti Lukats wrote:> "Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag > news:42e58544$1@clear.net.nz... >>>"Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> schrieb im Newsbeitrag >>>news:42e540a2$0$8024$3b214f66@tunews.univie.ac.at... >>>>Just looked at the sources - There are binary VHDL files. What does >>>>this mean? >>>> >>>>Martin >>>This means they can only be used by ISE tools. There should be no problems >>>using those files with ISE 6.2 to 7.1, just add to your project and >>>synthesise as normal. If there are any problems let me know. >> >>?! - do you mean you cannot save as ASCII source code, or use any other >>editor ? >> Surely this nonsense can be disabled ? >> >>-jg > Sure, ask for commercial licensing and you will get readable source code > instantly. > At the moment the sources are encrypted to prevent modification.I think I miss-understood your first reply - I thought this was some new 'ISE feature', but it seems it is something you can enable/disable, to password IP sources, until paid - correct ? -jg
Reply by ●July 26, 20052005-07-26
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:42e69666$1@clear.net.nz...> Antti Lukats wrote: > > "Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag > > news:42e58544$1@clear.net.nz... > >>>"Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> schrieb im Newsbeitrag > >>>news:42e540a2$0$8024$3b214f66@tunews.univie.ac.at... > >>>>Just looked at the sources - There are binary VHDL files. What does > >>>>this mean? > >>>> > >>>>Martin > >>>This means they can only be used by ISE tools. There should be noproblems> >>>using those files with ISE 6.2 to 7.1, just add to your project and > >>>synthesise as normal. If there are any problems let me know. > >> > >>?! - do you mean you cannot save as ASCII source code, or use any other > >>editor ? > >> Surely this nonsense can be disabled ? > >> > >>-jg > > Sure, ask for commercial licensing and you will get readable source code > > instantly. > > At the moment the sources are encrypted to prevent modification. > > I think I miss-understood your first reply - I thought this was some > new 'ISE feature', but it seems it is something you can enable/disable, > to password IP sources, until paid - correct ? > -jg >correct. until paid for source license. Antti
Reply by ●July 26, 20052005-07-26
Antti Lukats wrote:>> I think I miss-understood your first reply - I thought this was some >>new 'ISE feature', but it seems it is something you can enable/disable, >>to password IP sources, until paid - correct ? >>-jg >> > > correct. until paid for source license...and the price for that is.. ? -jg
Reply by ●July 26, 20052005-07-26
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:42e6a20d$1@clear.net.nz...> Antti Lukats wrote: > >> I think I miss-understood your first reply - I thought this was some > >>new 'ISE feature', but it seems it is something you can enable/disable, > >>to password IP sources, until paid - correct ? > >>-jg > >> > > > > correct. until paid for source license. > > ..and the price for that is.. ? > -jg >ok, as you asked then introductory offer - 1 company wide source code use license for the OCO library components for Spartan-3 2 free license for the clock analyzer application so you can perform the measurement accross chips and vcc/temp as needed 3 free license for the freq measurement ip cores (for the sw app) 4 free update/updgrade for Spartan-3E - as soon as we get S3E silicon for measurements and testing 5 tech support for instantition and use of the ip cores (per email) ==== 50 USD per paypal to antti@openchip.org Antti
Reply by ●July 27, 20052005-07-27
how often does an external clock fail? what king of the clock is it? how much useful to have an FPGA to backup? -Franklin
