After having mailed Altera which forwarded the mail to whoever... BTW it was rather hard to find an email adress at all to send such a question to. There is a pin error in the footprint of the EP2C8F256. The F5, LVDS13p is alone, there is no LVDS13n, which has to be for a true LVDS channel. Can anyone confirm this ? It basically means there is no LVDS13. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
Datasheet error in the Altera Cyclone 2C8F256 pindescription
Started by ●July 27, 2005
Reply by ●July 27, 20052005-07-27
> There is a pin error in the footprint of the EP2C8F256. > The F5, LVDS13p is alone, there is no LVDS13n, > which has to be for a true LVDS channel. > > Can anyone confirm this ? It basically means there > is no LVDS13.There is a LVDS13n on the Q208 package (which also has a LVDS13p).
Reply by ●July 27, 20052005-07-27
Hi Rene Tschaggelar,> After having mailed Altera which forwarded the mail to > whoever... BTW it was rather hard to find an email > adress at all to send such a question to. > > There is a pin error in the footprint of the EP2C8F256. > The F5, LVDS13p is alone, there is no LVDS13n, > which has to be for a true LVDS channel. > > Can anyone confirm this ? It basically means there > is no LVDS13.Well, Quartus says: Error: Can't place node positive with differential I/O zort2 in location (0,17,2) -- location does not support differential pin pair functionality Error: Can't place I/O pin zort2(n) in non-bonded location PAD_7 Error: Can't fit design in device So I guess something is indeed wrong. Rene, will you file the SR or shall I do it? Best regards, Ben
Reply by ●July 27, 20052005-07-27
Ben Twijnstra wrote:> Hi Rene Tschaggelar, > > >>After having mailed Altera which forwarded the mail to >>whoever... BTW it was rather hard to find an email >>adress at all to send such a question to. >> >>There is a pin error in the footprint of the EP2C8F256. >>The F5, LVDS13p is alone, there is no LVDS13n, >>which has to be for a true LVDS channel. >> >>Can anyone confirm this ? It basically means there >>is no LVDS13. > > > Well, Quartus says: > > Error: Can't place node positive with differential I/O zort2 in location > (0,17,2) -- location does not support differential pin pair functionality > Error: Can't place I/O pin zort2(n) in non-bonded location PAD_7 > Error: Can't fit design in device > > So I guess something is indeed wrong. > > Rene, will you file the SR or shall I do it?file what & where ? Ah, support request ? That is this personal login stuff ? A black hole, IMO. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
Reply by ●July 27, 20052005-07-27
> There is a pin error in the footprint of the EP2C8F256. > The F5, LVDS13p is alone, there is no LVDS13n, > which has to be for a true LVDS channel. > > Can anyone confirm this ? It basically means there > is no LVDS13.Hi Rene, My answer was somewhat cryptive, the die pad LVDS13n is simply not available on this package. So it is available on the die, and in the Q208 package, but not in the F256 package. There it is replaced by some dedicated pins for config.
Reply by ●July 27, 20052005-07-27
> file what & where ? > Ah, support request ? That is this personal login stuff ? > A black hole, IMO. >Not necessarily: I have got two bugs fixed that way, one with the next service-pack, for one I even got a patch within a few days. However, I have to admit that I also had that feeling ("black hole") in the past. It depends on who handles your request, and you need some patience. But I think it has improved during the last year... I think a SR is the right thing for your question as I suppost that noone here can tell you more than you can guess yourself (just use another LVDS pair that has p and n ;-)... Thomas
Reply by ●July 27, 20052005-07-27
Hi Thomas,>> file what & where ? >> Ah, support request ? That is this personal login stuff ?Yep.>> A black hole, IMO.Not entirely. I have over 300 SRs on my account since 2000 that have been fixed by now. Most of them even within an agreeable timeframe. I will not make any further quantitative or qualitative remarks about Altera's support service - it sort of works for me. Anyway, I filed SR#10507655 with the following text regarding version 1.3 of the EP2C8 pin table: ==== Cut here ==== For the EP2C8, in the F256 package, on page 1, pin F5 is listed as LVDS13p. However, there is no corresponding LVDS13n for this package. If I assign signal zort2 to pin F5 using LVDS as an IO standard, Quartus II 5.0SP1 reports the following: Error: Can't place node positive with differential I/O zort2 in location (0,17,2) -- location does not support differential pin pair functionality Error: Can't place I/O pin zort2(n) in non-bonded location PAD_7 Error: Can't fit design in device Can you add a remark for the F256 package about this? ==== Cut here ==== Let's see what happens... Best regards, Ben
Reply by ●July 28, 20052005-07-28
Hi guys, The Quartus error message is correct. The I/O cell (on the FPGA die) which implements the positive I/O of LVDS channel 13 is bonded out to Pin F5 on the EP2C8F256. However, the I/O cell which implements the negative I/O of the LVDS channel 13 differential pair is not bonded out on this package. I am not sure of the precise reason -- there are many goals and restrictions when a package pin-out is chosen. The effect is that you cannot use LVDS channel 13 in the EP2C8F256. Pin F5 is usable for non-LVDS purposes (i.e. as a general I/O). The EP2C8Q208 has both the negative and positive I/O cells of LVDS channel 13 bonded out, so LVDS channel 13 is usable in that device/package combo. Regards, Vaughn Altera [v b e t z (at) altera.com] "Ben Twijnstra" <btwijnstra@gmail.com> wrote in message news:2a222$42e7a6a2$d55db008$28922@news.chello.nl...> Hi Thomas, > >>> file what & where ? >>> Ah, support request ? That is this personal login stuff ? > > Yep. > >>> A black hole, IMO. > > Not entirely. I have over 300 SRs on my account since 2000 that have been > fixed by now. Most of them even within an agreeable timeframe. I will not > make any further quantitative or qualitative remarks about Altera's > support > service - it sort of works for me. > > Anyway, I filed SR#10507655 with the following text regarding version 1.3 > of > the EP2C8 pin table: > > ==== Cut here ==== > For the EP2C8, in the F256 package, on page 1, pin F5 is listed as > LVDS13p. > However, there is no corresponding LVDS13n for this package. > > If I assign signal zort2 to pin F5 using LVDS as an IO standard, Quartus > II > 5.0SP1 reports the following: > > Error: Can't place node positive with differential I/O zort2 in location > (0,17,2) -- location does not support differential pin pair functionality > Error: Can't place I/O pin zort2(n) in non-bonded location PAD_7 > Error: Can't fit design in device > > Can you add a remark for the F256 package about this? > ==== Cut here ==== > > Let's see what happens... > > Best regards, > > > Ben >
Reply by ●July 28, 20052005-07-28
Hi Vaughn,> The Quartus error message is correct.Yep. A remark saying something like "(1) Pin only supports single-ended I/O standards in F256 and T144 packages" would be helpful in rev 1.4. Updated my SR accordingly to clarify. Best regards, Ben
Reply by ●August 16, 20052005-08-16
Hello everyone, The EP2C8 device pin-out file (http://www/literature/dp/cyclone2/ep2c8.pdf) displays information for all available packages. There is a row for each pin and the information in the column for the device package specifies the package pin number. If the pin does not appear in a specific package, the corresponding spreadsheet cell is left blank. The pin in question has an optional function LVDS13p and is identified by pin number 8 for the Q208 package and pin number F5 for the F256 package. As mentioned earlier in the thread, the negative pair LVDS13n is available only in the Q208 package displayed as pin 10 and is intentionally left blank for the F256 package indicating that this pin was not bonded out to the package. The Quartus II software issues an error message if you assign a pin with a differential I/O standard to pin number F5. I agree it's not clear that pin number F5 (optional function LVDS13p) only supports single-ended I/O standards. The current version of the pin-out file relies on readers to notice that there is no pin with an optional function LVDS13n in the F256 package. To help clarify this issue, I have requested a footnote be added to an upcoming version of the pin-out documents. As Ben suggested, the footnote will indicate pin number F5 is available only as a single-ended I/O standard because the negative pin for the LVDS channel 13 is not available. By the way, if you use the Quartus II Pin Planner or Timing Closure Floorplan Editor when planning your FPGA IOs, you can turn on Show Differential Pin Pair Connections (View menu) to display a connection between the members of each differential pin pair. Albert Chang Senior Applications Engineer Altera Corporation
