I develop systems were the FPGA-based hardware will use message-based communication
(via Ethernet, USB or another communication channel) with remote software. Those
systems require thorough testing in simulations.
Therefore I needed to create a mechanism for communication between the simulation
and software using the remote message-passing library like ZeroMQ.
The first version was implemented for GHDL, using VHPI, and it was very simple:
Unfortunately, sometimes my systems have to use proprietary Xilinx IP blocks, that
can't be simulated with GHDL.
(Especially now, when Xilinx decided to postpone support for VHLD models for IP
The only option to interface simulation with the external C library in Vivado XSIM
is now DPI via SystemVerilog.
(Well, it is possible to communicate via named pipes and sockets, but it requires
reimplementation of ZeroMQ in HDL, which quite complex)
Because it is not possible to directly communicate with SystemVerilog functions in
tasks from VHDL, I had to create a simple module (entity), that provides a standard
signal-based interface for VHDL. There are two equivalent versions. One for GHDL and
another one for XSIM. The sources are also available at
The code is just "proof of the concept", so it is not very clean. However, I hope
that it may be useful or at least inspiring for somebody,
The code is published as Public Domain or under Creative Commons CC0 license, so it
may be widely reused.
I'll appreciate any suggestions for improvements or bugs fixes.
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