Gentlemen: I have a situation where some of my compatriots want to be able to reset a Virtex2 in order to reload the program from the 18V04 chips. Generally, they are going to want to do this after they have loaded a new image into the eprom's and they want to do it under program control. Would I be correct in assuming that all they need to do is instantiate glbl.v in their design and assert the GSR signal hi? At that point, the chip should tri-state that same assertion and all the other signals, read the eproms and start afresh? Charles
GSR
Started by ●July 7, 2003
Reply by ●July 8, 20032003-07-08
GSR sets the internal registers to their initial state. If you want to reconfigure you need to drive the oe/reset pin of the prom then the prog_b of the fpga. You can do this from the fpga itself. Steve "Charles Krinke" <someone@pacbell.net> wrote in message news:UhlOa.161$q%6.95@newssvr16.news.prodigy.com...> Gentlemen: > I have a situation where some of my compatriots want to be able toreset> a Virtex2 in order to reload the program from the 18V04 chips. Generally, > they are going to want to do this after they have loaded a new image into > the eprom's and they want to do it under program control. > > Would I be correct in assuming that all they need to do is instantiate > glbl.v in their design and assert the GSR signal hi? At that point, thechip> should tri-state that same assertion and all the other signals, read the > eproms and start afresh? > > Charles > >