Chipscope pro : timing constraint?

dear chip scope pro users

Problem with VIO occurred in ChipScope Pro, ISE6.3.

i am (still -: ) exercising VIO,IlA with "asynchronous reset,
asynchronous enable, 4 bit counter"

It works fine in ILA. That is the signal changes " 0 1 2 3 4 ...."

Problem is that, in VIO console, the signal behavior is not the same as
ILA. That is the signal changes " 2 9 3 0 9 7 ...", which is
unexpected.

I am not still sure that this behavior in VIO is problematic or not.

BTW, during implementation, following warnings occured. (1) and (3)
seem to be okay to ignore, but (2) seems to be problematic.

Does anyone has this experience? Why the signal behavior in VIO is
different from ILA?

----------------------------
(1)WARNING:Timing:2666 - Constraint ignored: PATH "FROM U_CLK TO D_CLK"
 TIG ;
(2)WARNING:Timing:2665 - clk does not clock any primary output
(3)WARNING:Timing:2666 - Constraint ignored: OFFSET = IN 5 nS  BEFORE
COMP "clk" ;
All constraints were met.
----------------------------

############################
### UCF file
############################
NET "clk" LOC = "AJ15";
NET "cnt<0>" LOC = "AD13";
NET "cnt<1>" LOC = "AD12";
NET "cnt<2>" LOC = "AD11";
NET "cnt<3>" LOC = "AD10";
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 10ns HIGH 50 %;
OFFSET = IN 5 ns BEFORE "clk";
OFFSET = OUT 6 ns AFTER "clk";

Pasacco wrote:
> dear chip scope pro users
> 
> Problem with VIO occurred in ChipScope Pro, ISE6.3.
> 
> i am (still -: ) exercising VIO,IlA with "asynchronous reset,
> asynchronous enable, 4 bit counter"
> 
> It works fine in ILA. That is the signal changes " 0 1 2 3 4 ...."
> 
> Problem is that, in VIO console, the signal behavior is not the same as
> ILA. That is the signal changes " 2 9 3 0 9 7 ...", which is
> unexpected.
> 
> I am not still sure that this behavior in VIO is problematic or not.
> 
> 

The VIO functionality and the ILA functionality are very different from
each other.

The ILA core captures data for every clock edge and presents the data to
the display when the buffer is full.

The VIO core allows you to insert control (inputs) and display sampled
status (outputs) similar to using a bank of push buttons or switches
for inputs or LEDs for outputs. There are arrows in the display for
that indicate activity occurred between the sampled points, so if the
previous value was 0 and the new value is 0 you can tell if blipped up
to a one and back again.

What you describe sounds like a normal sampling of the data set with a
free running counter.

Ed

Cycle accurate sampling can not be seen in VIO. That's was not a
problematic one. Thankyou for comment.

BTW, in the code below, I can not see the expected behavior of signal
'counter' in ILA.

Problem is that I only see : 4 4 4 4 .........

When rst = 0, en = 1, the signal change "0 1 2 3 4 " should be seen in
ILA waveform.
But actually so signal change can be seen.

What is the problem?
By the way, Is this problem?

Thankyou.

------------------------------------------------------------------------
-- Expected signal 'counter' behavior :  0 1 2 3 4 4 4 4 .....
------------------------------------------------------------------------
entity top is
port
(  clk : in std_logic;
   cnt : out std_logic_vector(3 downto 0)  );
end top;

architecture behave of top is
signal counter : std_logic_vector(3 downto 0):=(others=>'0');

signal rst, en: std_logic;            -- In VIO, reset=0, enable=1

begin
  process(en,rst,clk,counter)
  begin
   if en='0' then
       counter <= (others => '0');
   elsif rst='1' then
     counter <= (others => '0');
   elsif counter <= "0011" then
     if ( clk'event and clk = '1') then
        counter <= counter + 1;
     end if;
   end if;     
  end process;
  cnt <= counter(3 downto 0);
end behave;

Pasacco,

Your code is doing exactly what you asked it to do.  Your IF
statements do this.

   1) If en=0  then count=0
   2) If rst=1 then count=0
   3) If count < 3 then count = count + 1
   4) Else nothing

So when count=4 that's the end of the game.

Ed


Pasacco wrote:
> Cycle accurate sampling can not be seen in VIO. That's was not a
> problematic one. Thankyou for comment.
> 
> BTW, in the code below, I can not see the expected behavior of signal
> 'counter' in ILA.
> 
> Problem is that I only see : 4 4 4 4 .........
> 
> When rst = 0, en = 1, the signal change "0 1 2 3 4 " should be seen in
> ILA waveform.
> But actually so signal change can be seen.
> 
> What is the problem?
> By the way, Is this problem?
> 
> Thankyou.
> 
> ------------------------------------------------------------------------
> -- Expected signal 'counter' behavior :  0 1 2 3 4 4 4 4 .....
> ------------------------------------------------------------------------
> entity top is
> port
> (  clk : in std_logic;
>    cnt : out std_logic_vector(3 downto 0)  );
> end top;
> 
> architecture behave of top is
> signal counter : std_logic_vector(3 downto 0):=(others=>'0');
> 
> signal rst, en: std_logic;            -- In VIO, reset=0, enable=1
> 
> begin
>   process(en,rst,clk,counter)
>   begin
>    if en='0' then
>        counter <= (others => '0');
>    elsif rst='1' then
>      counter <= (others => '0');
>    elsif counter <= "0011" then
>      if ( clk'event and clk = '1') then
>         counter <= counter + 1;
>      end if;
>    end if;     
>   end process;
>   cnt <= counter(3 downto 0);
> end behave;
> 

Yes, it is correct.

In ILA, we can see the transition of the signal in a cycle accurate
manner.

BTW, What I want to see in ILA , in the example above, is

'counter' signal change (0 -> 1 -> 2 -> 3 -> 4 ) part.

Those transitions occur during the first 4 clock cycles, after (rst='0'
and en='1').

In my exercise, I do not see them. I only see the value '4', whih is
the last value.

Is it possible to see, in ILA, those signal transition behaviors in the
example above?

Pasacco wrote:
> Yes, it is correct.
> 
> In ILA, we can see the transition of the signal in a cycle accurate
> manner.
> 
> BTW, What I want to see in ILA , in the example above, is
> 
> 'counter' signal change (0 -> 1 -> 2 -> 3 -> 4 ) part.
> 
> Those transitions occur during the first 4 clock cycles, after (rst='0'
> and en='1').
> 
> In my exercise, I do not see them. I only see the value '4', whih is
> the last value.
> 
> Is it possible to see, in ILA, those signal transition behaviors in the
> example above?
> 

I don't understand what you are looking for or what problem you
are having.  You will need to explain it better for me to be able to
help you.

Also after reviewing your VHDL code again it is not written
in the standard way to define a registered counter and I am
not sure what would actually be synthesized in the design.

Specifically, you have any asynchronous comparison function
(counter <= "0001") before the clock edge definition
(clk'event and clk='1').  I'm not sure what would synthesized
with this code, probably a gated clock, but it likely won't
be what you intended.

Ed

Pasacco wrote:
> When rst = 0, en = 1, the signal change "0 1 2 3 4 " should be seen in
> ILA waveform.
> But actually so signal change can be seen.
>
> What is the problem?
> By the way, Is this problem?
>
> Thankyou.
>
> ------------------------------------------------------------------------
> -- Expected signal 'counter' behavior :  0 1 2 3 4 4 4 4 .....
> ------------------------------------------------------------------------
> entity top is
> port
> (  clk : in std_logic;
>    cnt : out std_logic_vector(3 downto 0)  );
> end top;
>
> architecture behave of top is
> signal counter : std_logic_vector(3 downto 0):=(others=>'0');
>
> signal rst, en: std_logic;            -- In VIO, reset=0, enable=1
>
> begin
>   process(en,rst,clk,counter)
>   begin
>    if en='0' then
>        counter <= (others => '0');
>    elsif rst='1' then
>      counter <= (others => '0');
>    elsif counter <= "0011" then
>      if ( clk'event and clk = '1') then
>         counter <= counter + 1;
>      end if;
>    end if;
>   end process;
>   cnt <= counter(3 downto 0);
> end behave;

Yikes ... I don't know what the synthesis tool will do, but I suspect
it won't do what you want!  Did you get any synthesis warnings?  Did
you read the synthesis manual?

-a

Hi

According to synthesis/implementation report, there is no indication
that the clock is gated.

This example is just an exercise.
My intention is just to make the value of an internal signal 'counter'
change " 0->1->2->3->4" and see that in ChipScope Pro.

Problem is that the ILA core captures only static value '4',   even
though 'RST' and 'EN' signal are driven by VIO "on the fly".

If it is possible to see the change of the value, instead of a static
value, I am doing something wrong.  What am I missing?

Thankyou.

Pasacco wrote:
> Hi
> 
> According to synthesis/implementation report, there is no indication
> that the clock is gated.
> 
> This example is just an exercise.
> My intention is just to make the value of an internal signal 'counter'
> change " 0->1->2->3->4" and see that in ChipScope Pro.
> 
> Problem is that the ILA core captures only static value '4',   even
> though 'RST' and 'EN' signal are driven by VIO "on the fly".
> 
> If it is possible to see the change of the value, instead of a static
> value, I am doing something wrong.  What am I missing?
> 
> Thankyou.
> 

You sent me more information on this in email and added another note
here. Try doing this.

1) In the ILA window change the trigger condition to a falling edge
    transition of the RESET line instead of the static low that you
    have now.

2) In the VIO window pulse the RESET button

3) Go back to the ILA window and you should see 0, 1, 2, 3, 4, 4, 4, 4...

Ed

Hi

Falling edge trigger, and now it works. Thankyou for nice comment and
correction.

With gratitude