Send IP packets at the Ethernet level with VIRTEX4

Hello,
I would to use a simple/easy way to send, in multicast address, some IP
packets
fprm a FPGA Xilinx VIRTEX4 to a Ethernet network. But I don't want to
use the
PowerPC and its EMAC controller. I read that the PHY interface can be
set in hardware register but I don't know if I can use the PHY
interface as a simple
FIFO.
Is there someone who uses that way to send IP packets to a network.
I know it is strange ... but I just want to read some IP paquets define
into my FPGA.
Best regards
Philippe

pho wrote:
> Hello,
> I would to use a simple/easy way to send, in multicast address, some IP
> packets
> fprm a FPGA Xilinx VIRTEX4 to a Ethernet network. But I don't want to
> use the
> PowerPC and its EMAC controller. I read that the PHY interface can be
> set in hardware register but I don't know if I can use the PHY
> interface as a simple
> FIFO.
> Is there someone who uses that way to send IP packets to a network.
> I know it is strange ... but I just want to read some IP paquets define
> into my FPGA.

Howdy Philippe,

   Yes, it is pretty simple to compose a packet of your choice and have
the FPGA feed it to a phy (either an internal phy to the FPGA or an
external xMII-type phy).  phy's have simple FIFO interfaces with a
small amount of extra signalling to indicate SOP, EOP, and idle times.
A V2Pro works as well as a V4 for this type of thing.

The easiest way would be to have a BRAM initialized with the packet
that you want to send.  When given a go signal by software, a counter
can be kicked off to automaticly read the contents of the BRAM, feeding
each byte to the phy.  And since BRAM's are dual-port, the next step
would be to allow read/write access to that packet in real time -
allowing the destination address (or any other byte in the packet) to
be modified on the fly.

Be sure your counter stops reading at the end of the BRAM and doesn't
wrap around to zero, continously flooding your local network with
packets (hopefully that isn't your goal to begin with).

   Marc

In article <1124872726.737546.229630@o13g2000cwo.googlegroups.com>,
pho <philippe.hostiou@orange.fr> wrote:
>Hello,

>I would to use a simple/easy way to send, in multicast address, some
>IP packets fprm a FPGA Xilinx VIRTEX4 to a Ethernet network. But I
>don't want to use the PowerPC and its EMAC controller. I read that
>the PHY interface can be set in hardware register but I don't know if
>I can use the PHY interface as a simple FIFO.

Actually, its the MAC you want to use, not the PHY.  THere is a fair
amount of overhead/complexity in the PHY layer which the MAC abstracts
into "Send data stream/receive data stream".

The V4-FX Tri-mode MAC can be accessed in a raw mode, without the
powerPC.  You want to use the raw client MAC interface to do this
sending.  See the users guide for this: 
http://direct.xilinx.com/bvdocs/userguides/ug074.pdf

(starting at page 33)

It's not that hard (it's VERY similar to the raw client GEMAC core
that xilinx has available: 

For sending, you have a data valid signal, you get a data aack signal
and you start clocking the data a byte at a time.  

Likewise, for receiving, you get a data valid signal, you clock in the
data a word at a time.

If you are in full duplex mode, you don't even have to worry about
collisions, just send the data.
-- 
Nicholas C. Weaver.  to reply email to "nweaver" at the domain
icsi.berkeley.edu