Issues with Synplify Pro 7.7 synthesis

Hello All,

I am a graduate student in Computer Engineering an am developing some
small VHDL modules targeted to Xilinx Virtex devices. While I was
trying to synthesize some of those designs using synpliciy I got the
following error." Invalid LUT instantiation. Have you included the
virtex.v(hd) file, and an INIT value @E:Internal Error". I tried adding
virtex.vhd from synplicity installation library and tried to re
synthesize it and now I see an error " Undefined identifier" and it
does not even point to the module which causes this. I have read in
some other postings in this group that one should not include unisim
libraries while synthesizing using Synplify pro 7.7. I have in fact
tried both ways (including and excluding unisim libraries) but the
above error persists. I would appreciate if anyone can suggest where I
am doing wrong.

Thanks
Harish

Did you instantiate a LUT2, LUT3, or LUT4 primitive?
Did you provide an INIT value on that primitive?
How did you apply the INIT?

It may be a simple mistake in the complete instantiation.

"Harish Vutukuru" <harish.vutukuru@gmail.com> wrote in message
news:1125023514.907773.224250@z14g2000cwz.googlegroups.com...
> Hello All,
>
> I am a graduate student in Computer Engineering an am developing some
> small VHDL modules targeted to Xilinx Virtex devices. While I was
> trying to synthesize some of those designs using synpliciy I got the
> following error." Invalid LUT instantiation. Have you included the
> virtex.v(hd) file, and an INIT value @E:Internal Error". I tried adding
> virtex.vhd from synplicity installation library and tried to re
> synthesize it and now I see an error " Undefined identifier" and it
> does not even point to the module which causes this. I have read in
> some other postings in this group that one should not include unisim
> libraries while synthesizing using Synplify pro 7.7. I have in fact
> tried both ways (including and excluding unisim libraries) but the
> above error persists. I would appreciate if anyone can suggest where I
> am doing wrong.
>
> Thanks
> Harish
>

Hello ,

It was a simple error from my side. I included the Unisim libraries
between synthesis translate_off and translate_on. Once I remvoed those
it works fine

Thanks