CPLD Jitter

The dividers and the phase detector of my experimental frequency synthesizer
are implemented in a 15ns Altera MAX7000S CPLD.  I've tried different
multiplication factors (kN) to see how the close-in phase noise varies.  At
a 1 KHz offset, I get:

-82 dBc/Hz for N=198 (VCO=19.8 MHz, comparison freq = 100 KHz)
-95 dBc/Hz for N=39 (VCO=19.5 MHz, comparison freq = 500 KHz)

Calculating the equivalent phase noise at the PFD:

-82-20*log10(198) = -128 dBc/Hz
-95-20*log10(39) = -127 dBc/Hz

Given the 5:1 ratio of comparison frequencies, at a guess, I'd expect these
to differ by 13 dB if the noise was mainly due to a fixed amount of time
jitter at the PFD.

I'm using a 10 MHz canned crystal oscillator, which I'm dividing down
(inside the CPLD) to obtain the reference frequencies.  I've read these are
good for at least -130 dBc/Hz (before dividing down) so I'm a bit
dissappointed with my noise levels.  Maybe it got a bit too hot when I
soldered it to the ground plane!  I must try another....

Googling for "altera cpld jitter" doesn't turn-up much, and they don't
mention jitter in the datasheet.  Does anyone know what sort of performance
can be expected from a CPLD in this regard?  I don't know if the CPLD, or my
circuit lash-up is the root cause.

A full write-up of the project can be found at
http://www.holmea.demon.co.uk/Frac2/Main.htm  It has a fractional-N
capability, but noise-levels are the same in integer-N mode with the
external RAM disabled.

Thanks,
Andrew.

In article <desmbt$i07$1$8302bc10@news.demon.co.uk>,
Andrew Holme <andrew@nospam.com> wrote:
[...]
>Googling for "altera cpld jitter" doesn't turn-up much, and they don't
>mention jitter in the datasheet.  Does anyone know what sort of performance
>can be expected from a CPLD in this regard?  I don't know if the CPLD, or my
>circuit lash-up is the root cause.

If you have other signals running through the CPLD, part of the problem 
could be crosstalk.  Power supply noise will also show up as a jitter.

There seems to be a bad solder joint in the upper left corner.

Check the LM78M05 for oscillations. We don't see the traces hooking up the 
bypasses on it.  


You also have to be careful when making things like flip-flop phase
comparitors inside the MAX series.  When I made one, I had to add some 
extra logic after the flip-flops so that the "both" state of the flip-flop 
pair was used to gate off the output.  I think the CLRN timing was the 
problem bit once I got it working, I stopped looking for the root cause.

IIRC:

BothLatch = (UpFlipFlop # DownFlipFlop) & BothLatch
             #  UpFlipFlop & DownFlipFlop;

Up = UpFlipFlop & !DownFlipFlop & !BothLatch;


>
>A full write-up of the project can be found at
>http://www.holmea.demon.co.uk/Frac2/Main.htm  It has a fractional-N
>capability, but noise-levels are the same in integer-N mode with the
>external RAM disabled.
>
>Thanks,
>Andrew.
>
>


-- 
--
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>I'm using a 10 MHz canned crystal oscillator, which I'm dividing down
>(inside the CPLD) to obtain the reference frequencies.  I've read these are
>good for at least -130 dBc/Hz (before dividing down) so I'm a bit
>dissappointed with my noise levels.  Maybe it got a bit too hot when I
>soldered it to the ground plane!  I must try another....

Can you measure the raw oscillator output?

It may not be as good as you expect.  Many low volume oscillators
now use a PLL.  They program the dividers rather than grind the crystal
to get custom frequencies.

I'd expect that numbers like 10 MHz would have enough volume so that
they would avoid the PLL but maybe it's cheaper to have one production
setup and use it for the common frequencies too.

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other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
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I would suggest inserting a 100 ohm resistor between C3 and C7 and placing
a 100uF capacitor in parallel with C7.  The noise on the output of U4 is
just as critical as the noise on the + input of U3.

You may also want to add an RC filter on the output of U5 before feeding
it to U6.

Daniel Lang

"Andrew Holme" <andrew@nospam.com> wrote in message 
news:desmbt$i07$1$8302bc10@news.demon.co.uk...
> The dividers and the phase detector of my experimental frequency 
> synthesizer
> are implemented in a 15ns Altera MAX7000S CPLD.  I've tried different
> multiplication factors (kN) to see how the close-in phase noise varies. 
> At
> a 1 KHz offset, I get:
>
> -82 dBc/Hz for N=198 (VCO=19.8 MHz, comparison freq = 100 KHz)
> -95 dBc/Hz for N=39 (VCO=19.5 MHz, comparison freq = 500 KHz)
>
> Calculating the equivalent phase noise at the PFD:
>
> -82-20*log10(198) = -128 dBc/Hz
> -95-20*log10(39) = -127 dBc/Hz
>
> Given the 5:1 ratio of comparison frequencies, at a guess, I'd expect 
> these
> to differ by 13 dB if the noise was mainly due to a fixed amount of time
> jitter at the PFD.
>
> I'm using a 10 MHz canned crystal oscillator, which I'm dividing down
> (inside the CPLD) to obtain the reference frequencies.  I've read these 
> are
> good for at least -130 dBc/Hz (before dividing down) so I'm a bit
> dissappointed with my noise levels.  Maybe it got a bit too hot when I
> soldered it to the ground plane!  I must try another....
>
> Googling for "altera cpld jitter" doesn't turn-up much, and they don't
> mention jitter in the datasheet.  Does anyone know what sort of 
> performance
> can be expected from a CPLD in this regard?  I don't know if the CPLD, or 
> my
> circuit lash-up is the root cause.
>
> A full write-up of the project can be found at
> http://www.holmea.demon.co.uk/Frac2/Main.htm  It has a fractional-N
> capability, but noise-levels are the same in integer-N mode with the
> external RAM disabled.
>
> Thanks,
> Andrew.
>
> 

Hello Andrew,

> I'm using a 10 MHz canned crystal oscillator, which I'm dividing down
> (inside the CPLD) to obtain the reference frequencies.  I've read these are
> good for at least -130 dBc/Hz (before dividing down) so I'm a bit
> dissappointed with my noise levels. ...

Check its data sheet. If it doesn't have any noise specs on there get a 
better one. Or better yet, roll your own. CTS is a good source though.

> http://www.holmea.demon.co.uk/Frac2/Main.htm

How are the Altera GND pins connected to the plane? I can't see any 
connections. If that is via traces that's the first easy thing to fix.

Look at your VCC. Switch the scope to AC and crank it way up. When 
called out to clients that is were I found the main contributors for 
phase noise. Video line sync, RAM banking spikes, whatever, it all ended 
up adding a little AM modulation to the logic output stages which in 
turn causes jitter.

Sometimes others thought now I'd gone crazy: It often helps to take a 
very good comm receiver, put on tight fitting headphones and listen to 
your signals. Both sidebands plus wide open w/o IF filter. Often that 
revealed the tiny telltale "weeeee" or "rat-tat-tat". A spectrum 
analyzer on the pins and also on VCC can help as well.

Then there is the usual, such as 0.01uF caps tightly fitted from VCC 
pins (all of them) to the ground plane. Also, check what else is 
happening in the FPGA. As Ken wrote this could cause crosstalk, 
especially if other outputs are heavily loaded or must drive longer traces.

Regards, Joerg

http://www.analogconsultants.com

Andrew,
>
> Does anyone know what sort of performance can be expected
> from a CPLD in this regard?
>
  Asides from the supply/clocking suggestions already made,
I'd also add the following caution: the output stages of most
programmable digital parts are not intended for producing
clean reference signals to a PLL used for low-noise RF signal
generation.

 A few times over the years that I've considered doing this,
the first thing I've done is build something like a pulse output
divide-by-ten in the intended technology, driven the part with an
oscillator having known phase noise, and looked at the divider output
on both a spectrum analyzer & phase noise measurement system.

 Most of the programmable parts I've measured have had output spurs
50-60 db down that vary strongly in frequency with supply voltage,
and can cross over the intended output frequency, making it impossible
to keep them out of the loop BW. ( also, the crud in the output
spectrum will generally behave differently with an even duty cycle
output than for a pulse output divider )

 other (hastily conceived) random thoughts:
  - what's the noise floor of your spectrum analyzer at 1 KHz?
  - try using a surplus ocxo for your 10 MHz source
  - if you disable the uC/SRAM, and implement a fixed divide entirely
    internal to the CPLD, does the noise get any better?

have fun,
Brian

Thanks to all for the suggestions.

The ground pins were connected by threading wires through the holes, and
soldering them to the ground plane before fitting the PLCC socket.

Personally, I now think the monolithic regulator supplying U4 is the main
noise source.  Thanks, Daniel.  I've been pouring over Rohde and Egan,
trying to get my head round spectral density stuff.  I'd appreciate it if
someone could check my math.  I've calculated the equivalent noise voltage
that would have to be injected at the loop filter input (U4 output) to
produce -95 dBc/Hz at a 1 KHz offset on the VCO.  The following script was
executed in SCILAB:

// Closed-loop gain from PFD output to VCO output
pd_2_vco = h/kpd/kn;

// -95 dBc/Hz
theta_rms = sqrt(10^(-95/10) * 2);

// Equivalent noise injection at PFD output (1 KHz offset)
v_rms = theta_rms / horner(pd_2_vco, 2*%pi*1000)

This gives 20nV/sqrt(Hz).  Since U4 output is a 50% duty cycle square
wave(XOR PFD), presumably I would still only need 40nV/sqrt(Hz) on the
regulator output?  Is 40nV/sqrt(Hz) at 1 KHz credible for a 78L05 with 100n
+ 10n hanging off its output?

Script notes:
h = Closed loop gain
kpd = PFD gain
kn = Divider gain
horner() returns magnitude of transfer function at specified freq

Andrew Holme wrote:
> regulator output?  Is 40nV/sqrt(Hz) at 1 KHz credible for a 78L05
> with 100n + 10n hanging off its output?

The 78L05 datasheet quotes an output noise voltage of 40uV for 10Hz <= f <=
100 KHz with a minimum recommended load capacitance of 10n.  I presume this
means 40uV peak-to-peak?  I'm not sure how to convert this to RMS
nV/sqrt(Hz), but 40e-6/sqrt(100e3) = 1.26e-7 which is only 3 times my
figure.

Andrew Holme wrote:
> // Closed-loop gain from PFD output to VCO output
> pd_2_vco = h/kpd/kn;

Sorry, I think that was wrong.  That h was the closed-loop gain from ref
input to vco output.

A safer way to calculate it, using the SCILAB /. operator is:

t_pd_vco = (f * kvco/s)  /. (kpd * kn);

where f = loop filter transfer function.

Now I get v_rms = 793 nV/sqrt(Hz)

Hmm....

Andrew Holme wrote...
> Andrew Holme wrote:
>> regulator output?  Is 40nV/sqrt(Hz) at 1 KHz credible for a 78L05
>> with 100n + 10n hanging off its output?
>
> The 78L05 datasheet quotes an output noise voltage of 40uV for
> 10Hz <= f <= 100 KHz with a minimum recommended load capacitance
> of 10n.  I presume this means 40uV peak-to-peak? 

 Hah, it's likely rms, because that leads to a much smaller number.
 Also, the NEC and Linfinity datasheets explicitly say rms.

 The NSC datasheet note says, "minimum load capacitance of 0.01&#4294967295;F
 to limit high frequency noise," which means the output noise is
 not white, which means you can't perform the usual simple sqrt-BW
 calculations to obtain the noise density.  


-- 
 Thanks,
    - Win