Xilinx Virtex II fpga - providing single ended signal to lvds defined pin

Hello, I am having ADI board containing xilinx virtex II chip. There
are two pins defined as LVDS_33 I/O but I wanted to reprogram them as
single ended signals and hence I had removed the 100ohm resistance
between the lvds signals. The lvds receiver output signals are ignored
by my design. Hence I am sending two single ended signals to the two
pins which are defined as lvds.

Now the 2 pins take 0-2.4V and the other is open. Does this mean I am
exceeding the electrical ratings ?

I see this on the LVDS DC specifications.

VCCO =3D 3.3V

DC PARAMETER       CONDITION                 MIN  TYP   MAX
VIDIFF           (Common-mode I/p =3D 1.25)    100  350   N/A mV
I/p Common-Mode   (Diff I/p V=3D =B1350 mV)      0.2  1.25  VCCO - 0.5

I know I can redefine the pins to accept LVCMOS25 I/O but the way it
is, will it cause the device to fail ?