XilinX MAC FIR

Hi everybody,
I'm working on a small project in which we want basically to filter
Input data (Input Data Rate = 105Mhz) with a FIR filter (64
coefficients).
I've forseen to use the MAC FIR IP provided by Xilinx but there could
be a problem in the way input data are sampled.

Indeed, MAC FIR IP provides an output named RFD(Ready For Data) which
indicates when the MAC FIR can accept new data.

Does that mean ND (New Data signal) can't be stay at '1' to put new
data in FIR at each rising edge of clock sample (105 MHz)?

Since my Input data flow is unbroken, how can I do to process this
flow in real time?

Is there other free FIR IP more suitable for my application?

Thank you in advance for your answers.


PS: I'm a french guy, so I hope my english is not too bad and you will
able to understand what I mean ...  :oops:

Hi,

> I'm working on a small project in which we want basically to filter
> Input data (Input Data Rate = 105Mhz) with a FIR filter (64
> coefficients).
> I've forseen to use the MAC FIR IP provided by Xilinx but there could
> be a problem in the way input data are sampled.

A MAC FIR is not ideally suited to your application, given those parameters.
At a clock rate of (say) 210MHz, you would need 32 parallel MAC units to
keep up with the data input rate. This is virtually a full-parallel FIR
implementation. Of course your achievable clock rate will depend on what
part you are targeting.

You should probably still be able to use the Xilinx core, as it is capable
of using multiple MAC units according to your data rate requirements.
Provided that you configure the core such that it has enough processing
power to keep up, the handshaking on the data input samples will cause you
no problems.

Cheers,

        -Ben-

You can do this very easily for the cost of $595 US.   Just buy a
Xilinx ML-403 board, and a couple of 32x3 .100" connectors to get the data
in and out of the board.   The XC4VSX35 fpga on the card has 192 hardware
multipliers and adders, arranged in 2 columns of 96 each.   One column
should suffice for your requirements, and it will run as a 96 tap FIR
filter at 400 MHz.   Getting data in & out at 400 MHz would probably
require using LVDS, but 105 MHz should be relatively easy using CMOS 3.3V
or other single ended signaling.   You'll probably spend more time
getting the IO timing right than on the FIR filter, which can be generated
as a monolithic core by the Coregen tool.  You really don't want to use
the MAC FIR, by the way.  Just a standard FIR will work fine.

John

The ISE 7.1 coregen 

On Tue, 13 Sep 2005 19:17:03 -0500, seb_tech_fr wrote:

> Hi everybody,
> I'm working on a small project in which we want basically to filter
> Input data (Input Data Rate = 105Mhz) with a FIR filter (64
> coefficients).
> I've forseen to use the MAC FIR IP provided by Xilinx but there could
> be a problem in the way input data are sampled.
> 
> Indeed, MAC FIR IP provides an output named RFD(Ready For Data) which
> indicates when the MAC FIR can accept new data.
> 
> Does that mean ND (New Data signal) can't be stay at '1' to put new
> data in FIR at each rising edge of clock sample (105 MHz)?
> 
> Since my Input data flow is unbroken, how can I do to process this
> flow in real time?
> 
> Is there other free FIR IP more suitable for my application?
> 
> Thank you in advance for your answers.
> 
> 
> PS: I'm a french guy, so I hope my english is not too bad and you will
> able to understand what I mean ...  :oops:

Ben, John,

Thank you for your replies.

John, I think, as you said, MAC FIR is not relally suited for my
application. And since I have an XC2VP30, the best is to manually
program a FIR filter by myself. I think it's could be not too
difficult.

Ben, I agree with you (a s I said above). Concerning the hadrware
Platform, it's an ADM-XPL board of
Alpha-Data with a XC2VP30-5.

Thank you