I have designed a small module usilng vhdl.I converted this module
using IPIF and created an IP.Now I added this IP into my design as a
master/slave module to the OPB bus.I have to inititate a transaction
from my module to the OPB busi.e I want to send some data to the slave
module connected to the opb bus.
One thing I have noticed is that there is no M_Dbus as output of IPIF
to OPB bus.
I enable the IP2Bus_Wrreq(user logic to IPIF) high and wait for the
BUS2IP_wrack signal.But nothing happens.Also there is no change in the
M_request signal of the IPIF(on the OPB bus side)which is steady at 0
The following is the IPIF wrapper:
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to
C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to
C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to
C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to
C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
M_ABus : out std_logic_vector(0 to
C_OPB_AWIDTH-1);
M_BE : out std_logic_vector(0 to
C_OPB_DWIDTH/8-1);
M_busLock : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_select : out std_logic;
M_seqAddr : out std_logic;
OPB_errAck : in std_logic;
OPB_MGrant : in std_logic;
OPB_retry : in std_logic;
OPB_timeout : in std_logic;
OPB_xferAck : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
What could be the problem.Is there some other signal that thas to be
tken care of?
Is there some other way other than IPIF that I can add my module as a
master on the OPB bus.
Thanks,
Nitesh
OPB bus communication
Started by ●September 20, 2005
Reply by ●September 21, 20052005-09-21
Hello Nitesh, I think you might want to consider adding an OPB arbiter. Even after adding the OPB arbiter you might get some problems assigning different masters an ID (C_DEV_BLK_ID) value to have the arbiter identify the respective masters. I just posted this messages today and if I get an answer it might be of some help to you or you might be able to help me with my issue: (thanks in advance) Hello all, I want to create an IP master on the OPB. I am using Xilinx Virtex2 (xc2v2000), and Xilinx platform studio (EDK) version 7.1.02i on the Xilinx Multimedia Board. I have tried looking everywhere for my answer and after a week of time-well-experienced I decided to ask the experts. I have a MicroBlaze (MB) as a master, an RS232 (UART) as a slave, LEDs (GPIO) as a slave, and memory as slave. I wanted to add my own IP master on the OPB. I created the IP using the "Create/Import Peripheral" wizard. I have tested my IP (simulation) and it works fine. Once I attach it to the bus, my IP doesn't seem to be executing anything. So I used ChipScope Pro 7.1i (Which is an amazing tool to analyze in-board signals) to tap into my request and acknowledge signals. What I noticed is that my IP doesn't seem to ever get an acknowledge. It Requested a read but never gets an acknowledge. So I realized, since there are more than one master on the bus I have to add an OPB arbiter. I added the OPB arbiter, but now I only get 16 characters on my RS232 output and no more LEDs flashing and if I tap into my IP signals I still see that my request has not been acknowledged. Can some please give me any direction? Thank you very much in advance. A side question, I noticed that the arbiter needs a device block ID (C_DEV_BLK_ID) parameter from every master on the OPB to identify them respectively. Where is this device block ID parameter for the MB and what other parameters do I have to set on the arbiter and custom IP. Peace, Moh Nitesh wrote:> I have designed a small module usilng vhdl.I converted this module > using IPIF and created an IP.Now I added this IP into my design as a > master/slave module to the OPB bus.I have to inititate a transaction > from my module to the OPB busi.e I want to send some data to the slave > module connected to the opb bus. > > One thing I have noticed is that there is no M_Dbus as output of IPIF > to OPB bus. > > I enable the IP2Bus_Wrreq(user logic to IPIF) high and wait for the > BUS2IP_wrack signal.But nothing happens.Also there is no change in the > M_request signal of the IPIF(on the OPB bus side)which is steady at 0 > The following is the IPIF wrapper: > port > ( > -- ADD USER PORTS BELOW THIS LINE ------------------ > --USER ports added here > -- ADD USER PORTS ABOVE THIS LINE ------------------ > > -- DO NOT EDIT BELOW THIS LINE --------------------- > -- Bus protocol ports, do not add to or delete > OPB_Clk : in std_logic; > OPB_Rst : in std_logic; > Sl_DBus : out std_logic_vector(0 to > C_OPB_DWIDTH-1); > Sl_errAck : out std_logic; > Sl_retry : out std_logic; > Sl_toutSup : out std_logic; > Sl_xferAck : out std_logic; > OPB_ABus : in std_logic_vector(0 to > C_OPB_AWIDTH-1); > OPB_BE : in std_logic_vector(0 to > C_OPB_DWIDTH/8-1); > OPB_DBus : in std_logic_vector(0 to > C_OPB_DWIDTH-1); > OPB_RNW : in std_logic; > OPB_select : in std_logic; > OPB_seqAddr : in std_logic; > M_ABus : out std_logic_vector(0 to > C_OPB_AWIDTH-1); > M_BE : out std_logic_vector(0 to > C_OPB_DWIDTH/8-1); > M_busLock : out std_logic; > M_request : out std_logic; > M_RNW : out std_logic; > M_select : out std_logic; > M_seqAddr : out std_logic; > OPB_errAck : in std_logic; > OPB_MGrant : in std_logic; > OPB_retry : in std_logic; > OPB_timeout : in std_logic; > OPB_xferAck : in std_logic > -- DO NOT EDIT ABOVE THIS LINE --------------------- > ); > > What could be the problem.Is there some other signal that thas to be > tken care of? > Is there some other way other than IPIF that I can add my module as a > master on the OPB bus. > Thanks, > Nitesh
Reply by ●September 23, 20052005-09-23
Hello Moh,
I have only one master So there is no problem of arbitration I guess.
The problem is that the M_request remains constant at '0'. with no
change even when I try to request a master write operation in my
user_logic.vhd
I enable my IP2bus_wrreq high place a valid address and data on the
IP2bus_addr,IP2bus_data,
IP2Bus_Retry <='0';
IP2Bus_Error <='0';
IP2Bus_ToutSup <='0';
IP2Bus_RdAck <='0';
IP2Bus_WrAck <='0';
My only doubt is what address should we assign to IP2IP_addr.
I think thta is the one which gives the problem.
There is absolutely no change in the signal on the OPS-IPIF side.
Thanks
Nitesh
Reply by ●September 23, 20052005-09-23
Nitesh wrote:> Hello Moh, > I have only one master So there is no problem of arbitration I guess. > > The problem is that the M_request remains constant at '0'. with no > change even when I try to request a master write operation in my > user_logic.vhd > > I enable my IP2bus_wrreq high place a valid address and data on the > IP2bus_addr,IP2bus_data, > IP2Bus_Retry <='0'; > IP2Bus_Error <='0'; > IP2Bus_ToutSup <='0'; > IP2Bus_RdAck <='0'; > IP2Bus_WrAck <='0'; > > My only doubt is what address should we assign to IP2IP_addr. > I think thta is the one which gives the problem.IP2IP_addr must be the address inside your ip address range where you want the data to be 'written' (or read). So if you ask for a master read from 0x10000000 (IP2Bus_addr) to 0x20000000 (IP2IP_addr) (with 0x2000000 being in the address range assigned to your IP), your slave interface will see signals as if someone was trying to write to 0x2000000 from the exterior. Not sure i'm very clear ... Sylvain
Reply by ●September 23, 20052005-09-23
I got that part.I have a user space of 256 bytes with 4 bytes per block.So the ip2ip_addr address which I am assigning is also correct but still I cannot get any change on M_request signal. I have gone through the opb manual and also the opb ipif signals manual but I still cannot figure out the solution.
