Prob in Synthesizing and Simulating large Mux

Every thing is correct. But i cant simply change my design. What i am
thinking now is to proceed with the 120 register version.
If required i can switch over to Virtex "XC2V8000". Will that help
(with 8M gates).
But i am still wondering why Xilinx is not doing any synthesizing work.
And about your code is there any way to implement the same in verilog.
I dont know VHDL.

Of course there is an identical way to implement VHDL in verilog...
unfortunately I don't know verilog either :-)
A XC2V8000 wow.. you must have a seriously huge budgie.. $8,300 each.. :-)

4 XC3S1000's would only cost you about $220. only 4,000 LUT's.. but I bet it
would fit too .. that's why I suggested using 4 FPGA's in the first place.


Simon


"vssumesh" <vssumesh_asic@yahoo.com> wrote in message
news:1128344153.831983.257240@g44g2000cwa.googlegroups.com...
> Every thing is correct. But i cant simply change my design. What i am
> thinking now is to proceed with the 120 register version.
> If required i can switch over to Virtex "XC2V8000". Will that help
> (with 8M gates).
> But i am still wondering why Xilinx is not doing any synthesizing work.
> And about your code is there any way to implement the same in verilog.
> I dont know VHDL.
>

The problem is i want that in a single chip. How can i link those huge
control signals out of FPGA.
But i am still wondering why the ISE is not working with my design. Ok
any way i am proceeding with 120 registers and will let all of you know
the results.
Thanks for all the advice and suggestions.

vssumesh wrote:
> The problem is i want that in a single chip. How can i link those huge
> control signals out of FPGA.
> But i am still wondering why the ISE is not working with my design.

Probably because your expectations are not inline with the device
capability?

You're trying to create a huge combinatorial mux.  It's not at all a
surprise that you're not meeting your timing requirements.

-a

you don't link.. you replicate!

Simon

"vssumesh" <vssumesh_asic@yahoo.com> wrote in message
news:1128426984.140362.116640@z14g2000cwz.googlegroups.com...
> The problem is i want that in a single chip. How can i link those huge
> control signals out of FPGA.
> But i am still wondering why the ISE is not working with my design. Ok
> any way i am proceeding with 120 registers and will let all of you know
> the results.
> Thanks for all the advice and suggestions.
>

I didn't understand that. How can i interconnect the huge routing
signals between the FPGA's.

one way is to simply  serialize the data using LVDS.. the other is to simply
replicate the input in each device the each device handles only 1/4 of the
selection.

Partly it depends on how/where your data is coming from.  I can't tell you
how to do it... you have to analyse and learn

Simon

"vssumesh" <vssumesh_asic@yahoo.com> wrote in message
news:1128515181.357701.217050@g47g2000cwa.googlegroups.com...
> I didn't understand that. How can i interconnect the huge routing
> signals between the FPGA's.
>