Altera NIOS PIO interrupt problem

Hello all,

I am monica from germany.I am using NIOS in cyclone FPGA.I have problem
with PIO interrupts.
Environment details

Quartus Software : version 4.2 build 178 01/19/2005 SJ full version
Nios software    : version 1.1.0 build 137
FPGA             : Altera cyclone

I have a input signal which should generate interrupt on every rising
edge.So I have used a PIO to capture the signal and generate the IRQ
for every rising edge.

PIO settings :
width : 1bit
direction : input only
Edge capture reg
synchronously capture : yes
rising edge :yes
generate irq : yes
edge : yes

The software hangs at
"alt_irq_register(TEST_CONTINUE_PIO_IRQ,(void
*)&global_flag,&intr_timer);"

However software works fine,If I change the PIO settings to

width : 1bit
direction : input only
Edge capture reg
synchronously capture : yes
rising edge :yes
generate irq : yes
level : yes

I am trying to find out what might be causing my software hang if I use
"edge" instead of "level".

Did anybody face this sort of wierd behaviour? or is this a bug in
Quartus software?

I have already wasted lot of time to find out a solution for this
problem.

I will be obliged if anybody can throw some light on this issue.

Thanking you,
Monica Dsouza

In the interrupt routine you need to clear the interrupt.
Check to see that you are doing that.

George