Data width change in opencores Ethernet MAC

Hello,

Just wondering if anyone can let me know if I'm going about this the
right way -

I'm trying to implement the opencores Ethernet MAC on a Xilinx FPGA,
but the board I have has too few I/Os. So, I want to reduce the width
of the 32bit data inputs and outputs in the wishbone interface to
accommodate (I'm about 70 IOBs short). It seems like this should be
feasible since the data is delivered to the interface in 1 byte chunks.
If I work around the byte counter and write the data to the FIFO right
away without assembling the bytes into 32bits...

I'm not so keen with verilog, so feel free to let me know if I'm going
about this all wrong, or if I'm forgetting something. Or you can tell
me I'm smoking something and that I should just not be cheap and get a
board that has enough IOs.

thanks!

pei

pei@uwiep.com wrote:
> Hello,
> 
> Just wondering if anyone can let me know if I'm going about this the
> right way -
> 
> I'm trying to implement the opencores Ethernet MAC on a Xilinx FPGA,
> but the board I have has too few I/Os. So, I want to reduce the width
> of the 32bit data inputs and outputs in the wishbone interface to
> accommodate (I'm about 70 IOBs short). It seems like this should be
> feasible since the data is delivered to the interface in 1 byte chunks.
> If I work around the byte counter and write the data to the FIFO right
> away without assembling the bytes into 32bits...
> 
> I'm not so keen with verilog, so feel free to let me know if I'm going
> about this all wrong, or if I'm forgetting something. Or you can tell
> me I'm smoking something and that I should just not be cheap and get a
> board that has enough IOs.
> 
> thanks!
> 
> pei
> 

You're putting the wishbone interface externally ? To connect it to what ?



	Sylvain