Re: ADC implementation on fpga? Information and procudures wanted.

Started by pingboypulsar<spamoff>@hotmail.com October 17, 2005
Yes i wish to interface to an external adc. 
Sorry if that was not clear. 

Hopefully the interfacing to an external adc is not too complicated.

I wish to be able to connect industrial sensor(s) to an adc, and 
then acquire the value to the fpga for further processing. Maybe its 
better to use an asic or something else for interfacing an adc. I 
need to find out these things.

Regards.
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On 17 Oct 2005 12:36:15 GMT, kd (pingboypulsar<spamoff>@hotmail.com)
wrote:

>Hopefully the interfacing to an external adc is not too complicated. > >I wish to be able to connect industrial sensor(s) to an adc, and >then acquire the value to the fpga for further processing. Maybe its >better to use an asic or something else for interfacing an adc. I >need to find out these things.
So, where's the hard part? You choose an external ADC based on the analog requirements - sampling rate, precision, aperture jitter, analogue bandwidth, and so on. You will probably find a lot of devices that meet your needs, so you must then refine the choice based on package size, cost, and complexity of the digital interface. Since you are doing industrial sensing stuff, I guess the data rate will be fairly low and it is probably sensible to choose a device with a serial interface (SPI or similar) because this will give you a smaller ADC package, use fewer pins on the FPGA, and make the circuit board layout much easier. OK, now you start to read the ADC data sheet carefully to decide what its digital data interface looks like. Now you have a straightforward digital design problem that can easily be solved in your FPGA. Use the FPGA to generate the ADC's clock (probably divided-down from your system clock), copy control register values out to the ADC, and read conversion results back. It's almost trivially easy. It would get harder if any of the following conditions applies: 1) Sampling rate of any one ADC is greater than about 50M samples/sec 2) Very large number of analogue inputs 3) Very high precision requirements (more than about 14 bits) 4) Need to maintain some special timing relationship between ADC sampling and something else, such as the activity of a DSP device Go away and try it. If you have trouble with some part, come back here and I'm sure someone will try to help. The rather vague nature of the responses so far has been directly related to the rather vague nature of your request :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.