RS232 Uart for Virtex-II Pro

Does anyone know if there's a ready-to-use rs232 uart in vhdl for the
Virtex-II pro fpga? We have done some designs in ISE, and hope to
display results in a terminal window. Thanks.

miniuart project at www.opencores.org is a ready-to use uart which
works very well. A more sophisticated one is in uart16550 project but
with miniuart is enough for most applications.

Javier Castillo

On 23 Oct 2005 21:17:06 -0700, "Eric" <dasani8888@hotmail.com> wrote:

>Does anyone know if there's a ready-to-use rs232 uart in vhdl for the
>Virtex-II pro fpga? We have done some designs in ISE, and hope to
>display results in a terminal window. Thanks.

Eric wrote:

>Does anyone know if there's a ready-to-use rs232 uart in vhdl for the
>Virtex-II pro fpga? We have done some designs in ISE, and hope to
>display results in a terminal window. Thanks.
>
>  
>
If it is transmit only, the design is very simple:  you need a shift 
register that gets reloaded every 10/11 bit times with the byte, and 
fixed start and stop bits.  The shift enable for the shift register has 
to be at the correct timing for the baud rate.  For that, you can use a 
DDFS, which is nothing more than an accumulator which adds a fixed 
increment to itself on each clock   The msb of the accumulator is your 
baud clock: synchronous edge detect that to obtain a shift enable for 
the shift register and your bit counter.  Here's a vhdl snippet:

             --DDFS generates bit clock from 50M clock
            ddfs<= ddfs + to_unsigned(ddfs_inc,20);     
            ddfs_z<= ddfs(ddfs'left);
            ddfs_re<= ddfs(ddfs'left) and not ddfs_z; --rising edge of  
bit clock
                  
            --UART transmitter
            if ddfs_re='1' then
                 --bit counter downcounts 9 downto -1
                if ubit(4)='1' or stopped='1' then --negative
                    ubit<= "01001";
                else
                    ubit<= ubit-1;
                end if;
               
                --uart shift register       
                --data output is start bit then data lsb first then 2 
stop bits.  Assuming driver inverts
                if ubit(4)='1' then
                    tx_register<= "11" & read_data & '0';
                else
                    tx_register<= '1' & tx_register(10 downto 1);
                end if;
            end if;

            serial_data_out<= tx_register(0);

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
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I have recoded a xilinx reference of UART and tested it in VIRTEX
II.The reference is in VHDL.And It can reach 115K when communication
with PC. If you interested it, you can contact me at
zhang.young@gmail.com.