Xilinx ISERDES

How many ISERDES are there in an FX12?

http://www.xilinx.com/products/tables/selector/index.htm

Depending on the package, there are either 240 or 320 available I/O,
and (almost) all of them have their own ISERDES.
Peter Alfke, Xilinx Applications

Thanks Peter.

If you need master-slave ISERDES to get 7 bits, are there any layout issues, 
pin assignment issues that would cause problems or crowding?  I only need 16 
ISERDES total.

Brad

No problem, not even with ten bits parallel.
Some of the configuration-oriented pins in the center do not have a
SerDes. that's why i wrote "almost". You will not run into any problems
in this regard.
Peter Alfke

Brad Smallridge wrote:
> Thanks Peter.
> 
> If you need master-slave ISERDES to get 7 bits, are there any layout issues, 
> pin assignment issues that would cause problems or crowding?  I only need 16 
> ISERDES total.

If you need a slave ISERDES, you 'borrow' the ISERDES from the other IOB 
in the tile. In that case, the other IOB has no ISERDES available. If 
you have single ended inputs, you couldn't have two 7-bit ISERDES on 2 
input pads in the same tile. If you have LVDS inputs you're OK because 
the 2 input pads form 1 internal signal that can feed to the 2 ISERDES 
in master-slave configuration.

It's pretty easy to see if you make up an example design, place and 
route then look at the results with FPGA editor.

---
Joe Samson (jsamson@)
PixelVelocity

Thank you Joseph,

I did what you suggested and did an example program. I am using LVDS inputs
and want 7:1 serdes.

The placement seems to be somewhat what you said in that the master iserdes
gets placed right next to the _p pad. The _n pad shows a single connection 
going
to the _p pad.  However the slave serdes seems to be placed willy-nilly, not 
in the
same tile, and sometimes mixed with a master iserdes of a different lvds 
signal in
the same tile.  Is there something you are doing to put the slave iserdes in 
the
same tile as the master, like a constraint?

Nice web site there.

Thanks,

Brad Smallridge
aivision.com

> If you need a slave ISERDES, you 'borrow' the ISERDES from the other IOB 
> in the tile. In that case, the other IOB has no ISERDES available. If you 
> have single ended inputs, you couldn't have two 7-bit ISERDES on 2 input 
> pads in the same tile. If you have LVDS inputs you're OK because the 2 
> input pads form 1 internal signal that can feed to the 2 ISERDES in 
> master-slave configuration.
>
> It's pretty easy to see if you make up an example design, place and route 
> then look at the results with FPGA editor.
> ---
> Joe Samson (jsamson@)
> PixelVelocity 

Brad Smallridge wrote:
> Thank you Joseph,
> 
> I did what you suggested and did an example program. I am using LVDS inputs
> and want 7:1 serdes.
> 
> The placement seems to be somewhat what you said in that the master iserdes
> gets placed right next to the _p pad. The _n pad shows a single connection 
> going
> to the _p pad.  However the slave serdes seems to be placed willy-nilly, not 
> in the
> same tile, and sometimes mixed with a master iserdes of a different lvds 
> signal in
> the same tile.  Is there something you are doing to put the slave iserdes in 
> the
> same tile as the master, like a constraint?

I just LOC'd the IO pins. I'm verifying the pinout of a new design, so I 
spent a few days trying out different banks and pin choices. I looked at 
almost every route in FPGA editor and only ever saw the master and slave 
paired with the two LVDS IOs. I'm using the reference design from 
XAPP705; maybe other logic is forcing the placement. There might be a 
timing spec that can only be satisfied if the ISERDES are in the same tile.

---
Joe

Peter Alfke wrote_
> No problem, not even with ten bits parallel.
What do I do if I need 12?

We use a lot of TI's ADS527X-ADCs, and those output 12bit-data-words
over LVDS-DDR-outputs running at 420MHz and higher. Up to now we have a
lot of fiddeling to do in Virtex-II Pro (see xapp774), so the ISERDES
seemed like the perfect solution. Only it seems that in
Master/Slave-Configuration, the maximum you can do is 10bit.

Is there any way to expand this, or do I have to do this "manually",
i.e. without the ISERDES, just like in Virtex-II Pro?

cu,
Sean

Sean Durkin schrieb:
> Peter Alfke wrote_
> 
>>No problem, not even with ten bits parallel.
> 
> What do I do if I need 12?
> 
> We use a lot of TI's ADS527X-ADCs, and those output 12bit-data-words
> over LVDS-DDR-outputs running at 420MHz and higher. 

So these are 6-bit nibbles at 70MHz. Should be easy with the ISERDES.

Kolja Sulimma