ISE5.2 to ISE6.1

Hi all,

I have updated my Xilinx software to 6.1 a few days ago and it
looks like I am in for a ride; the design that worked well under
the previous version (5.2 with all service packs) wouldn't even
go through PAR anymore!! I managed to work around this
by setting thr effort level to maximum for the place&route but
when I program the FPGA (XC2V4000-5) with this new bitstream
my board doesn't work anymore!!?
Anybody having similar problems?
I guess I shoild have known better: the service pack for this latest
software creation arrived before the CD with the software did!
In my humble oppinion the best software from Xilinx was 4.2,
it's all downhill from there; it seems that a nice GUI is valued more than
a decent and consistent PAR algorithm these days.
---
jakab

In article <bmp871$22k$1@news.storm.ca>,
 "jakab tanko" <jtanko@ics-ltd.com> writes:

|> Anybody having similar problems?

Me too. A design for a 2S200 which needs to run at 130MHz (5.1 achieved ~133MHz
without floorplaning) is slowed down with 6.1 to about 110MHz. "High effort" etc.
does not help at all. Looking at the timinganalyzer output, it seems that MAP
ignores the first carry chain block and uses regular logic and routing instead,
thus stealing about 2ns :-(

-- 
         Georg Acher, acher@in.tum.de
         http://wwwbode.in.tum.de/~acher
         "Oh no, not again !" The bowl of petunias

I've had similar problems.  A few here have mentioned the problem you
have.  I have a problem with timing not being met (was met on 5.2i)
even though I have several timing constraints and placement
constraints that should help.

I'd agree with your final statement, but it really isn't a 'nice GUI'.
 It's more like a slopped-together GUI to get the task done, but pays
little attention to the technical details that FPGA engineers desire
or the good GUI design that can provide such nice results.  As GUIs
go, it's most comparable to the crap that Matlab added to their 6.0
stuff.

And don't even get me started on ECS.  I've seen schematic capture
programs done as an assembly-language programming course final project
that are better than that.

   Jake

jakab tanko wrote:

> In my humble oppinion the best software from Xilinx was 4.2,
> it's all downhill from there; 

I agree. 4.2 had bugs, but it was possible to work around them. Trying 
to compile the same project under 5.x and 6.x is a disaster. The bugs 
are so bad that it won't even synthesize.

Georg Acher <acher@in.tum.de> wrote:
: In article <bmp871$22k$1@news.storm.ca>,
:  "jakab tanko" <jtanko@ics-ltd.com> writes:

: |> Anybody having similar problems?

: Me too. A design for a 2S200 which needs to run at 130MHz (5.1 achieved ~133MHz
: without floorplaning) is slowed down with 6.1 to about 110MHz. "High effort" etc.
: does not help at all. Looking at the timinganalyzer output, it seems that MAP
: ignores the first carry chain block and uses regular logic and routing instead,
: thus stealing about 2ns :-(

Perhaps send your code to Xilinx for inclusion in their regression test
suite. However after the VLGINCDIR happening ( it was broken until 5.2  and
is broken again in 6.1) I wonder if there is any...

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

I actually found the bugs in 4.2 to be show stoppers, where 5.2 at least
is sufficient to get the job done.  I've also had better results
achieiving tight timing with 5.2 than with 4.2.  I haven't evaluated 6.1
yet (mid project).  I'm only talking about the tools from translate on
however.  I use synplicity for synthesis, so I haven't compared XST for
recent xilinx versions.

Marc Guardiani wrote:

> jakab tanko wrote:
>
> > In my humble oppinion the best software from Xilinx was 4.2,
> > it's all downhill from there;
>
> I agree. 4.2 had bugs, but it was possible to work around them. Trying
> to compile the same project under 5.x and 6.x is a disaster. The bugs
> are so bad that it won't even synthesize.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

"jakab tanko" <jtanko@ics-ltd.com> writes:

> Hi all,
> 
> I have updated my Xilinx software to 6.1 a few days ago and it
> looks like I am in for a ride; the design that worked well under
> the previous version (5.2 with all service packs) wouldn't even
> go through PAR anymore!! 

Been there - done that, PAR just crashes now!  "Will be fixed in next
service pack" is as far as I can get with 6.1, so its back to 5.2 for
me!

<snip>

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Hi,
   I am facing the same problem. I have a design in XC2S400E which is
working well in ISE 5.1 sp3 and met all timing requirements. When I
moved to 5.2 it failed to give required timing. I did not worry b'coz
I knew that they are coming up with 6.1. Now when I
synthesized/implemented my design in 6.1 (latest sp), it is giving the
same result as in 5.2 (i.e. it is unable to meet the performance of
5.1).
   Now I am sticking with 5.1i since I have already used it for many
months, and also given my product to some customers (I need to support
them!!!).
   My gut feeling is that when they changed from 5.1 to 5.2 something
has gone wrong in the tool software, and when they upgraded to 6.1
since they used 5.2 (i assume! ) as base version, the problem
continued to exist even in 6.1. This is a clue to Xilinx people
(anybody here?) so that they can findout the cause of this problem.
   Could anybody give assurance that atleast next versions will be
free from critical problems like these?

Regards,
Nagaraj CS


"jakab tanko" <jtanko@ics-ltd.com> wrote in message news:<bmp871$22k$1@news.storm.ca>...
> Hi all,
> 
> I have updated my Xilinx software to 6.1 a few days ago and it
> looks like I am in for a ride; the design that worked well under
> the previous version (5.2 with all service packs) wouldn't even
> go through PAR anymore!! I managed to work around this
> by setting thr effort level to maximum for the place&route but
> when I program the FPGA (XC2V4000-5) with this new bitstream
> my board doesn't work anymore!!?
> Anybody having similar problems?
> I guess I shoild have known better: the service pack for this latest
> software creation arrived before the CD with the software did!
> In my humble oppinion the best software from Xilinx was 4.2,
> it's all downhill from there; it seems that a nice GUI is valued more than
> a decent and consistent PAR algorithm these days.
> ---
> jakab

I see a new post started about this elsewhere in this group.  My one
comment is that the FAEs who post here recommend that you call the
hotline and open a case on this.  The sooner they learn of your problem
the sooner they can address it and keep it from being *my* problem...
8^O


Nagaraj wrote:
> 
> Hi,
>    I am facing the same problem. I have a design in XC2S400E which is
> working well in ISE 5.1 sp3 and met all timing requirements. When I
> moved to 5.2 it failed to give required timing. I did not worry b'coz
> I knew that they are coming up with 6.1. Now when I
> synthesized/implemented my design in 6.1 (latest sp), it is giving the
> same result as in 5.2 (i.e. it is unable to meet the performance of
> 5.1).
>    Now I am sticking with 5.1i since I have already used it for many
> months, and also given my product to some customers (I need to support
> them!!!).
>    My gut feeling is that when they changed from 5.1 to 5.2 something
> has gone wrong in the tool software, and when they upgraded to 6.1
> since they used 5.2 (i assume! ) as base version, the problem
> continued to exist even in 6.1. This is a clue to Xilinx people
> (anybody here?) so that they can findout the cause of this problem.
>    Could anybody give assurance that atleast next versions will be
> free from critical problems like these?
> 
> Regards,
> Nagaraj CS
> 
> "jakab tanko" <jtanko@ics-ltd.com> wrote in message news:<bmp871$22k$1@news.storm.ca>...
> > Hi all,
> >
> > I have updated my Xilinx software to 6.1 a few days ago and it
> > looks like I am in for a ride; the design that worked well under
> > the previous version (5.2 with all service packs) wouldn't even
> > go through PAR anymore!! I managed to work around this
> > by setting thr effort level to maximum for the place&route but
> > when I program the FPGA (XC2V4000-5) with this new bitstream
> > my board doesn't work anymore!!?
> > Anybody having similar problems?
> > I guess I shoild have known better: the service pack for this latest
> > software creation arrived before the CD with the software did!
> > In my humble oppinion the best software from Xilinx was 4.2,
> > it's all downhill from there; it seems that a nice GUI is valued more than
> > a decent and consistent PAR algorithm these days.
> > ---
> > jakab

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

6.1 clearly has some problems. I recommend that you steer clear of it
until these problems are cleared up. I intalled it on 3 computers and
2 had problems. What tech support wanted me to do made no sense (strip
everything out of the path but xilinx). I am sorry, but I am not being
paid to debug Xilinx's problems.

Tom Seim