ISE5.2 to ISE6.1

Tom Seim wrote:
> 
> 6.1 clearly has some problems. I recommend that you steer clear of it
> until these problems are cleared up. I intalled it on 3 computers and
> 2 had problems. What tech support wanted me to do made no sense (strip
> everything out of the path but xilinx). I am sorry, but I am not being
> paid to debug Xilinx's problems.

Did you also install the service pack? 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
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"jakab tanko" <jtanko@ics-ltd.com> wrote in message news:<bmp871$22k$1@news.storm.ca>...
> Hi all,
> 
> I have updated my Xilinx software to 6.1 a few days ago and it
> looks like I am in for a ride; the design that worked well under
> the previous version (5.2 with all service packs) wouldn't even
> go through PAR anymore!! I managed to work around this
> by setting thr effort level to maximum for the place&route but
> when I program the FPGA (XC2V4000-5) with this new bitstream
> my board doesn't work anymore!!?
> Anybody having similar problems?
> I guess I shoild have known better: the service pack for this latest
> software creation arrived before the CD with the software did!
> In my humble oppinion the best software from Xilinx was 4.2,
> it's all downhill from there; it seems that a nice GUI is valued more than
> a decent and consistent PAR algorithm these days.
> ---
> jakab

       I have had problems with 5.1,5.2 and 6.1 on  XC2V4000 and
XC2V6000 designs. My original designs were done on 4.x.  I believe
that the problem is in migrating the 4.2 designs to 6.1.
       I use 4.2 to synthesize and route, and Impact 5.2 to program
the FPGAs.
       I have reported every problem to Xilinx.
       New designs that are originated using 6.1 work OK.

Bill Hanna