hex rep. in VHDL

hi,
I have a small query in VHDL language.
Like we write in Verilog
 fifo_data <= 16'hAA4F;
How can i write this in VHDL.????
The signal fifo_data is a vector of 16 bit length .
Writing it as
fifo_data <= 16#AA4F# gives a error when my signal is a
std_logic_vector.
If i change it to integer ,it works

anupam wrote:

> hi,
> I have a small query in VHDL language.
> Like we write in Verilog
>  fifo_data <= 16'hAA4F;
> How can i write this in VHDL.????
> The signal fifo_data is a vector of 16 bit length .

fifo_data <= X"AA4F";

Regards,
Mark

fifo_data <= X"AA4F";

This representation gives an error " expecting an expression of type
std_logic_vector"
Remember ,my fifo_data is a std_logic_vector.

regards,
Anupam Jain

anupam schrieb:
> fifo_data <= X"AA4F";
> 
> This representation gives an error " expecting an expression of type
> std_logic_vector"
> Remember ,my fifo_data is a std_logic_vector.
> 
> regards,
> Anupam Jain
> 
AFAIK this works only if the bus width is a integer multiple of four.

Regards
Falk

Anupam,
      X"AA4F" should work, which simulator do you use? I believe this
is a VHDL-93 feature and it is amazing that even in 2005 end (almost 13
years!!) some tools require a Mode-93 kind of switch to their
compilers.

Your compiler may need a -V93 or some thing similar.

HTH
Ajeetha
www.noveldv.com

I always use this(fifo_data <= X"AA4F")  kind of HEX
representation(assignment) for std_logic_vector and it works.
The 16#AA4F# is for variables I think.

Falk Brunner wrote:

>> fifo_data <= X"AA4F";
> AFAIK this works only if the bus width is a integer multiple of four.

Yes, it does, which is *really* annoying!!!

Why they dont allow something like...
	foo(4 downto 0) <= X"1F";
is beyond me!?!

Regards,
Mark

Mark McDougall wrote:

> Yes, it does, which is *really* annoying!!!

A dog barking all night or
an IRS audit is *really* annoying.

I can tolerate
  foo(4 downto 0) <= "11111";    -- or
  foo(4 downto 0) <= "1" & x"F";
to get compile time width checking
on all vectors.

         -- Mike Treseler

Mike Treseler wrote:

> I can tolerate
>  foo(4 downto 0) <= "11111";    -- or
>  foo(4 downto 0) <= "1" & x"F";
> to get compile time width checking
> on all vectors.

Warning #1034: X"1F" width 8 truncated to width 5 in assignment.

Regards,
Mark

On Tue, 01 Nov 2005 17:28:00 +1100, Mark McDougall 
<markm@vl.com.au> wrote:

>Warning #1034: X"1F" width 8 truncated to width 5 in assignment.

Here's the deal:  The hex notation X"1F" etc was a hack introduced
in VHDL-93 to answer users' concerns that they wanted a simple way
to write hex literals of vector type.  

<rant>

The "right" way to do it,
of course, is...

  ...
  use ieee.numeric_std.all;
  ...
  signal vec: std_logic_vector(4 downto 0);
  ...
  vec <= std_logic_vector(to_unsigned(#16#1F#, vec'length));

but that's kinda clumsy, and for some reason no-one ever
gets around to writing this rather trivial procedure:

  procedure copy_int_to_slv_signal (
    signal v: out std_logic_vector;
    n: in natural 
  ) is
  begin
    v <= std_logic_vector(to_unsigned(n, v'length));
  end;

so that I can now write

  copy_int_to_slv_signal(vec, #16#1F#);

</rant>

So the VHDL-93 writers gave in to popular opinion, but tried
to do it without adding too much hidden magic.  Consequently
they invented a rewriting rule such that the hex literal X"1F"
is simply macro-substituted with the string literal "00011111"
(each hex digit is replaced with four binary digits in the string).
This of course allows type-compatibility of a hex literal with
any vector whose element type includes the literals '0' and '1',
correctly matching BIT, STD_LOGIC_VECTOR and UNSIGNED among others.
But it forces any hex literal to have a multiple of four bits.

Note that std_logic_textio similarly requires all its 
std_logic_vector objects to be a multiple of four bits when
reading or writing in hex.

It really isn't a big deal.  Program your way around it by 
building a sensible set of application-specific utility 
functions and procedures.
-- 
Jonathan Bromley, Consultant

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