System Verilog Import package error

Hello,
I have a few packages that I have written like this:

package A;
-- 
--
endpackage

package B;
import A::*
---
-- 
endpackage

package C;
import A::*;
import B::*;
endpackage

In the file using package C, the error I am getting is as follows:
Error (10864): SystemVerilog error at C.sv(26): TMP was imported from multiple packages with ::* - none of the imported declarations are visible.

Is this problem because I am importing A::* in both package A and package C?
Any help to rsolve this is greatly appreciated.

Thanks in Advance~

--
Nikhil Pratap