Hi I have a PCI core from xilinx it's ucf is done for spartan-3-200 device want to port the same design to spartan-3e250 device. have changed the pin assignment but was getting the following error during place and route. " Phase 1.1 ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed." and there were timing errors too, how can i port the design to another device, may i get some direction to proceed in this regard Thanks in advance rgds bijoy
FPGA : PCI-CORE
Started by ●November 2, 2005
Reply by ●November 2, 20052005-11-02
When you buy the Core, you normally get a user Id and a passwd to access the private section in Xilinx website so that you can change the UCF online, I think? You can also contact the guy who sold you the core in the first place. Regards, -- Ignacio Ulises Hernandez " I'm not normally a praying man, but if you're up there, please save me, Superman!" - Homer Simpson ;O) "bijoy" <pbijoy@rediffmail.com> wrote in message news:ee916ad.-1@webx.sUN8CHnE...> Hi I have a PCI core from xilinx it's ucf is done for spartan-3-200 device > > want to port the same design to spartan-3e250 device. > > have changed the pin assignment but was getting the following error during > place and route. " Phase 1.1 ERROR:Place:207 - Due to SelectIO banking > constraints, the IOBs in your design cannot be automatically placed." and > there were timing errors too, > > how can i port the design to another device, may i get some direction to > proceed in this regard > > Thanks in advance > > rgds bijoy
Reply by ●November 2, 20052005-11-02
Hi First of all i would like to Thank You for your immediate response. The problem i am facing is different, we have got a PCI core from xilinx for demo purpose with a ucf and for spartan-3 200 device. Now we want to try the same in the spartan-3e-250 device due to some cost consideration, but pci core ucf generator is not available now with xilinx for this particular family, spartan-3e is relattiviely new and there is no ucf file made for porting PCI core to this device, so i have to manually do the ucf generation from the ucf given for the spartan-3-200 device. This is my real problem, i am trying all my option in my hand, but i am not familiar with the ucf files and especially for designs of pci core and its internal signals and the timing requuirements are not available to me. regards bijoy
Reply by ●November 2, 20052005-11-02
"bijoy" <pbijoy@rediffmail.com> schrieb im Newsbeitrag news:ee916ad.1@webx.sUN8CHnE...> Hi First of all i would like to Thank You for your immediate response. > > The problem i am facing is different, we have got a PCI core from xilinxfor demo purpose with a ucf and for spartan-3 200 device.> > Now we want to try the same in the spartan-3e-250 device due to some costconsideration, but pci core ucf generator is not available now with xilinx for this particular family, spartan-3e is relattiviely new and there is no ucf file made for porting PCI core to this device, so i have to manually do the ucf generation from the ucf given for the spartan-3-200 device.> > This is my real problem, i am trying all my option in my hand, but i amnot familiar with the ucf files and especially for designs of pci core and its internal signals and the timing requuirements are not available to me.> > regards bijoyhttp://cgi.ebay.de/ws/eBayISAPI.dll?ViewItem&item=5825643507 that e-book includes ALL instructions how to get an PCI design up and running. the PCI core used there is VERY simple and usually works out of box, you just assign PCI IO pins and constraint on PCI clock nothing else. I have tested the PCI core on spartan 3, virtex2, cyclone and max2 boards. its not a solution for your problem, but its an EASY way to test an existing PCI FPGA board. Antti
Reply by ●November 2, 20052005-11-02
> http://cgi.ebay.de/ws/eBayISAPI.dll?ViewItem&item=5825643507 > > that e-book includes ALL instructions how to get an PCI design up and > running. > the PCI core used there is VERY simple and usually works out of box, you > just assign PCI IO pins and constraint on PCI clock nothing else. > I have tested the PCI core on spartan 3, virtex2, cyclone and max2 boards.Antti, Does this clearly explain how to get an FPGA based PCI core to emulate an LPT port, and does the C++ include the code that talks to it? Nial.
Reply by ●November 2, 20052005-11-02
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> schrieb im Newsbeitrag news:4368d700$0$23295$db0fefd9@news.zen.co.uk...> > http://cgi.ebay.de/ws/eBayISAPI.dll?ViewItem&item=5825643507 > > > > that e-book includes ALL instructions how to get an PCI design up and > > running. > > the PCI core used there is VERY simple and usually works out of box, you > > just assign PCI IO pins and constraint on PCI clock nothing else. > > I have tested the PCI core on spartan 3, virtex2, cyclone and max2boards.> > > Antti, > > Does this clearly explain how to get an FPGA based PCI core to emulate > an LPT port, and does the C++ include the code that talks to it? >YES. it also includes a LPT connected logic analyzer (uses BRAM's). so original software written for LPT connected logic analyzer does run on the PCI board. the PCI LPT is 'Lava PCI LPT' it is recognized by Windows XP nativly no extra driver just regular LPT (with 16 base address !!!) any software that can talk to LPT can talk to the PCI core, and whatever is connected to the virtual LPT wires. I am using the same PCI-LPT with xilinx cable III emulation in MAX2 starterkit as PCI Xlinx Cable III :) Antti PS Nial, I have verified the PCI part of the cores on your cyclone board it worked. the LPT stuff is just later mods not verified on your cyclone board but I am confident it should work as well.
Reply by ●November 2, 20052005-11-02
"bijoy" <pbijoy@rediffmail.com> wrote in message news:ee916ad.-1@webx.sUN8CHnE...> Hi I have a PCI core from xilinx it's ucf is done for spartan-3-200 device > > want to port the same design to spartan-3e250 device. > > have changed the pin assignment but was getting the following error during > place and route. " Phase 1.1 ERROR:Place:207 - Due to SelectIO banking > constraints, the IOBs in your design cannot be automatically placed." and > there were timing errors too, > > how can i port the design to another device, may i get some direction to > proceed in this regard > > Thanks in advance > > rgds bijoyIt shouldn't be tough to get things running. If you look at the pad report generated during place & route, you'll find the banks and what the tool believes the VCCO should be for those banks. You may have an I/O from somewhere else in your design that wants to share a bank with the PCI pins but doesn't use the 3.3V. The Spartan-3E has a bunch of input-only pins that you need to keep track of since most of the PCI signals are I/O. Also, your config file has a bit that will put the "PCI_LOGIC" block back into use; the Spartan-3 dropped the feature but the Spartan-3E brought it back. You can look at FPGA Editor to see the expected placement of the I/Os relative to the PCI_LOGIC block assuming you're not using the free Xilinx tools (which don't have the FPGA Editor if I recall correctly).
Reply by ●November 2, 20052005-11-02
"John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag news:r16af.26$Ge6.159@news-west.eli.net...> "bijoy" <pbijoy@rediffmail.com> wrote in message > news:ee916ad.-1@webx.sUN8CHnE... >> Hi I have a PCI core from xilinx it's ucf is done for spartan-3-200 >> device >> >> want to port the same design to spartan-3e250 device. >> >> have changed the pin assignment but was getting the following error >> during place and route. " Phase 1.1 ERROR:Place:207 - Due to SelectIO >> banking constraints, the IOBs in your design cannot be automatically >> placed." and there were timing errors too, >> >> how can i port the design to another device, may i get some direction to >> proceed in this regard >> >> Thanks in advance >> >> rgds bijoy > > It shouldn't be tough to get things running. If you look at the pad > report generated during place & route, you'll find the banks and what the > tool believes the VCCO should be for those banks. You may have an I/O > from somewhere else in your design that wants to share a bank with the PCI > pins but doesn't use the 3.3V. > > The Spartan-3E has a bunch of input-only pins that you need to keep track > of since most of the PCI signals are I/O. Also, your config file has a > bit that will put the "PCI_LOGIC" block back into use; the Spartan-3 > dropped the feature but the Spartan-3E brought it back. You can look at > FPGA Editor to see the expected placement of the I/Os relative to the > PCI_LOGIC block assuming you're not using the free Xilinx tools (which > don't have the FPGA Editor if I recall correctly). >Hi John, the the PCI_LOGIC is undocumented FPGA primitive do you happen to have addtional info about it? is useable in non xilinx design by using hard macro wrapper around it or by other means? Antti
Reply by ●November 2, 20052005-11-02
Antti, I have no documentation on the functionality of the block. I only know that it's included or excluded in the Xilinx PCI cores through the PCI .cfg file. Others have wondered about explicit functionality before - you might find something with Google. Generally, it's used to provide clock enables to the data lines combinatorially based on the PCI interface IRDY and TRDY (and other core) signals since these have the most stressed timing in PCI. - John_H "Antti Lukats" <antti@openchip.org> wrote in message news:dkart4$h85$1@online.de...> Hi John, > > the the PCI_LOGIC is undocumented FPGA primitive do you happen to have > addtional info about it? > is useable in non xilinx design by using hard macro wrapper around it or > by other means? > > Antti
Reply by ●November 2, 20052005-11-02
Hi bijoy, My company Brace Design Solutions has developed a Xilinx (TM) LogiCORE (TM) PCI compatible (replacement) PCI IP core called BDS XPCI PCI IP core. While the current release of the BDS XPCI PCI IP core (Ver. 1.0.0) doesn't come with a constraint file for Spartan-3 or Spartan-3E, we have done Post Place & Route simulation of BDS XPCI PCI IP core in Spartan-3, and has functioned properly. Therefore, we should be able to port it to Spartan-3E relatively easily, and we can also specifically create a UCF constraint file for the particular Spartan-3E part you have. The BDS XPCI32 PCI IP core commercial perpetual license version normally costs $3,000 for domestic customers/$3,600 for foreign customers, but as an introductory pricing, we will offer it for $2,000 for domestic customers/$2,400 for foreign customers. Only the first few customers will get the introductory pricing, so if you are interested, we recommend that you contact us right away. For other interested ordinary FPGA users, we offer BDS XPCI32 PCI IP core is available for as little as $100 for non-commercial, non-profit, personal use, and the same 64-bit version BDS XPCI64 PCI IP core (Includes BDS XPCI32 PCI IP core) goes for $200. Since the pricing starts at only $100, it is ideal for HDL learners, FPGA beginners, FPGA hobbyists, computer hardware enthusiasts, or student graduation projects. BDS XPCI PCI IP core comes with a PCI testbench for Verilog HDL which allows the user to simulate the design extensively on HDL simulators before firing up the FPGA. ModelSim including ModelSim XE is supported by BDS XPCI PCI IP core, and the next release of BDS XPCI PCI IP core will support a $50 Verilog HDL simulator called Veritak by Sugawara Systems (http://www.sugawara-systems.com) as a low cost alternative to ModelSim XE. (Current version doesn't function properly in Veritak, but the problem has been fixed.) VHDL support is currently poor, but VHDL porting of reference designs and PCI testbench should be available in a month. (Porting has been taking a little longer than expected.) BDS XPCI PCI IP core officially supports the following PCI boards. - Insight Electronics Spartan-II 150 PCI (Already discontinued) - Insight Electronics Spartan-II 200 PCI Development Kit http://www.memec.com/uploaded/SpartanII200PCI.pdf BDS XPCI PCI IP core "unofficially" supports the following PCI boards. - Avnet Xilinx Spartan-3 Evaluation Kit http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D7816%2526CCD%253DUSA%2526SID%253D4742%2526DID%253DDF2%2526SRT%253D1%2526LID%253D18806%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html http://www.em.avnet.com/ctf_shared/evk/df2df2usa/Xilinx%20Spartan-3%20Evaluation%20Kit%20-%20Brief%20022504F.pdf - Enterpoint Broaddown2 Development Board http://www.enterpoint.co.uk/moelbryn/broaddown2.html So with BDS XPCI PCI IP core, almost anyone can make their own PCI device for about $450 to $550. ($300 to $400 for the board + $100 for BDS XPCI32 PCI IP core + $50 for Veritak.) For commercial users who want to modify a Xilinx LogiCORE PCI or want to convert a design that uses Xilinx LogiCORE PCI to an ASIC (FPGA to ASIC conversion), BDS XPCI PCI IP core is also available in Verilog HDL RTL. For more information, visit Brace Design Solutions website at http://www.bracedesignsolutions.com. Kevin Brace bijoy wrote:> Hi I have a PCI core from xilinx it's ucf is done for spartan-3-200 device > > want to port the same design to spartan-3e250 device. > > have changed the pin assignment but was getting the following error during place and route. " Phase 1.1 ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed." and there were timing errors too, > > how can i port the design to another device, may i get some direction to proceed in this regard > > Thanks in advance > > rgds bijoy-- Brace Design Solutions Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available for as little as $100 for non-commercial, non-profit, personal use. http://www.bracedesignsolutions.com Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.
