Hi, I had this error in Xilinx ISE 7.1 but I cannot understand why, or what
to do about it.
Any help appreciated.
Thanks,
-Andrew
Release 7.1.04i Map H.42
Xilinx Mapping Report File for Design 'xilinxchip_original'
Design Information
------------------
Command Line : C:/Xilinx/bin/nt/map.exe -ise
c:\xilinx\bin\pv4_004mfsd_127\original.ise -intstyle ise -p
xc4vlx60-ff668-12
-cm area -detail -pr b -k 4 -c 100 -o xilinxchip_original_map.ncd
xilinxchip_original.ngd xilinxchip_original.pcf
Target Device : xc4vlx60
Target Package : ff668
Target Speed : -12
Mapper Version : virtex4 -- $Revision: 1.26.6.4 $
Mapped Date : Sun Oct 30 23:20:44 2005
Design Summary
--------------
Number of errors : 1
Number of warnings :1132
Section 1 - Errors
------------------
ERROR:Pack:1142 - A problem was encountered updating the component types
within
the following shape:
The RPM "uChip0_Cal1_XA1_TA0/hset"
A problem was encountered trying to change the type of the component
containing the following symbols to "SLICEL".
LUT symbol "uChip0_Cal1_XA1_TA0/BU1006" (Output Signal =
uChip0_Cal1_XA1_TA0/N56436) (RLOC=X5Y10, Set=uChip0_Cal1_XA1_TA0/hset)
Shift symbol "uChip0_Cal1_XA1_TA0/BU1014" (Output Signal =
uChip0_Cal1_XA1_TA0/N56799) (RLOC=X5Y10, Set=uChip0_Cal1_XA1_TA0/hset)
FLOP symbol "uChip0_Cal1_XA1_TA0/BU1017" (Output Signal =
uChip0_Cal1_XA1_TA0/N720) (RLOC=X5Y10, Set=uChip0_Cal1_XA1_TA0/hset)
The component is already of type "SLICEM". The setting of the component
type
is necessary since it is an odd number of columns away from a component
which
already has a type of "SLICEM". This second component contains the
following
symbols:
Shift symbol "uChip0_Cal1_XA1_TA0/BU996" (Output Signal =
uChip0_Cal1_XA1_TA0/N56748) (RLOC=X4Y10, Set=uChip0_Cal1_XA1_TA0/hset)
FLOP symbol "uChip0_Cal1_XA1_TA0/BU999" (Output Signal =
uChip0_Cal1_XA1_TA0/N56731) (RLOC=X4Y10, Set=uChip0_Cal1_XA1_TA0/hset)
Shift symbol "uChip0_Cal1_XA1_TA0/BU1001" (Output Signal =
uChip0_Cal1_XA1_TA0/N56768) (RLOC=X4Y10, Set=uChip0_Cal1_XA1_TA0/hset)
FLOP symbol "uChip0_Cal1_XA1_TA0/BU1004" (Output Signal =
uChip0_Cal1_XA1_TA0/N56430) (RLOC=X4Y10, Set=uChip0_Cal1_XA1_TA0/hset)
This architecture has two types of components, SLICELs and SLICEMs, in
alternating columns. Only SLICEMs can contain RAM symbols.
Anybody understand this ISE 7.1 error, and what to do about it???
Started by ●November 4, 2005
Reply by ●November 4, 20052005-11-04
"Andrew Lohbihler" <xyz.interactive@rogers.com> schrieb im Newsbeitrag news:TfCdndMvzOo2TPbenZ2dnUVZ_tGdnZ2d@rogers.com...> Hi, I had this error in Xilinx ISE 7.1 but I cannot understand why, or > what to do about it. > Any help appreciated. > Thanks, > -Andrewyour desing requires for some reason SLICEMs to be placed at invalid relative positions. This is the error saying. Why it happens I can not tell, some problem with placement constraints. Antti
Reply by ●November 4, 20052005-11-04
Unlike earlier Virtex family devices, the Virtex-4 has half the slices allowed as memory-capable. The RPM cannot have shift registers or distributed CLB SelectRAM (single port or dual port) in both odd AND even RLOC columns. The SLICEL has a lookup table that's logic only while the SLICEM has LUTs that can be loaded and read as a single port memory, a dual-port memory, or a shift register. If the RPM was done for a project in a Virtex-IIPro or older device, you'll need to tweak it for the "odd or even column only" constraint of the Virtex-4. If your RPM is fresh for this design, simply reconfigure it for the constraint you now know is getting in your way. - John_H "Andrew Lohbihler" <xyz.interactive@rogers.com> wrote in message news:TfCdndMvzOo2TPbenZ2dnUVZ_tGdnZ2d@rogers.com...> Hi, I had this error in Xilinx ISE 7.1 but I cannot understand why, or > what to do about it. > Any help appreciated. > Thanks, > -Andrew > > > Release 7.1.04i Map H.42 > Xilinx Mapping Report File for Design 'xilinxchip_original' > > Design Information > ------------------ > Command Line : C:/Xilinx/bin/nt/map.exe -ise > c:\xilinx\bin\pv4_004mfsd_127\original.ise -intstyle ise -p > xc4vlx60-ff668-12 > -cm area -detail -pr b -k 4 -c 100 -o xilinxchip_original_map.ncd > xilinxchip_original.ngd xilinxchip_original.pcf > Target Device : xc4vlx60 > Target Package : ff668 > Target Speed : -12 > Mapper Version : virtex4 -- $Revision: 1.26.6.4 $ > Mapped Date : Sun Oct 30 23:20:44 2005 > > Design Summary > -------------- > Number of errors : 1 > Number of warnings :1132 > Section 1 - Errors > ------------------ > ERROR:Pack:1142 - A problem was encountered updating the component types > within > the following shape: > The RPM "uChip0_Cal1_XA1_TA0/hset" > A problem was encountered trying to change the type of the component > containing the following symbols to "SLICEL". > LUT symbol "uChip0_Cal1_XA1_TA0/BU1006" (Output Signal = > uChip0_Cal1_XA1_TA0/N56436) (RLOC=X5Y10, Set=uChip0_Cal1_XA1_TA0/hset) > Shift symbol "uChip0_Cal1_XA1_TA0/BU1014" (Output Signal = > uChip0_Cal1_XA1_TA0/N56799) (RLOC=X5Y10, Set=uChip0_Cal1_XA1_TA0/hset) > FLOP symbol "uChip0_Cal1_XA1_TA0/BU1017" (Output Signal = > uChip0_Cal1_XA1_TA0/N720) (RLOC=X5Y10, Set=uChip0_Cal1_XA1_TA0/hset) > The component is already of type "SLICEM". The setting of the component > type > is necessary since it is an odd number of columns away from a component > which > already has a type of "SLICEM". This second component contains the > following > symbols: > Shift symbol "uChip0_Cal1_XA1_TA0/BU996" (Output Signal = > uChip0_Cal1_XA1_TA0/N56748) (RLOC=X4Y10, Set=uChip0_Cal1_XA1_TA0/hset) > FLOP symbol "uChip0_Cal1_XA1_TA0/BU999" (Output Signal = > uChip0_Cal1_XA1_TA0/N56731) (RLOC=X4Y10, Set=uChip0_Cal1_XA1_TA0/hset) > Shift symbol "uChip0_Cal1_XA1_TA0/BU1001" (Output Signal = > uChip0_Cal1_XA1_TA0/N56768) (RLOC=X4Y10, Set=uChip0_Cal1_XA1_TA0/hset) > FLOP symbol "uChip0_Cal1_XA1_TA0/BU1004" (Output Signal = > uChip0_Cal1_XA1_TA0/N56430) (RLOC=X4Y10, Set=uChip0_Cal1_XA1_TA0/hset) > This architecture has two types of components, SLICELs and SLICEMs, in > alternating columns. Only SLICEMs can contain RAM symbols. >
Reply by ●November 5, 20052005-11-05
Thanks John, The code did work for a Virtex-II and the details of the packing don't indicate which column constraint was used. Any idea what constraint should be changed to make it work in a Virtex-4? There must be a way to tweak the design for the V4 to make it pack similarily as a V2. Any help will do. Thanks, Andrew "John_H" <johnhandwork@mail.com> wrote in message news:YMQaf.57$Ge6.296@news-west.eli.net...> Unlike earlier Virtex family devices, the Virtex-4 has half the slices > allowed as memory-capable. The RPM cannot have shift registers or > distributed CLB SelectRAM (single port or dual port) in both odd AND even > RLOC columns. The SLICEL has a lookup table that's logic only while the > SLICEM has LUTs that can be loaded and read as a single port memory, a > dual-port memory, or a shift register. > > If the RPM was done for a project in a Virtex-IIPro or older device, > you'll need to tweak it for the "odd or even column only" constraint of > the Virtex-4. If your RPM is fresh for this design, simply reconfigure it > for the constraint you now know is getting in your way. > > - John_H > > > "Andrew Lohbihler" <xyz.interactive@rogers.com> wrote in message > news:TfCdndMvzOo2TPbenZ2dnUVZ_tGdnZ2d@rogers.com... >> Hi, I had this error in Xilinx ISE 7.1 but I cannot understand why, or >> what to do about it. >> Any help appreciated. >> Thanks, >> -Andrew >> >> >> Release 7.1.04i Map H.42 >> Xilinx Mapping Report File for Design 'xilinxchip_original' >> >> Design Information >> ------------------ >> Command Line : C:/Xilinx/bin/nt/map.exe -ise >> c:\xilinx\bin\pv4_004mfsd_127\original.ise -intstyle ise -p >> xc4vlx60-ff668-12 >> -cm area -detail -pr b -k 4 -c 100 -o xilinxchip_original_map.ncd >> xilinxchip_original.ngd xilinxchip_original.pcf >> Target Device : xc4vlx60 >> Target Package : ff668 >> Target Speed : -12 >> Mapper Version : virtex4 -- $Revision: 1.26.6.4 $ >> Mapped Date : Sun Oct 30 23:20:44 2005 >> >> Design Summary >> -------------- >> Number of errors : 1 >> Number of warnings :1132 >> Section 1 - Errors >> ------------------ >> ERROR:Pack:1142 - A problem was encountered updating the component types >> within >> the following shape: >> The RPM "uChip0_Cal1_XA1_TA0/hset" >> A problem was encountered trying to change the type of the component >> containing the following symbols to "SLICEL". >> LUT symbol "uChip0_Cal1_XA1_TA0/BU1006" (Output Signal = >> uChip0_Cal1_XA1_TA0/N56436) (RLOC=X5Y10, Set=uChip0_Cal1_XA1_TA0/hset) >> Shift symbol "uChip0_Cal1_XA1_TA0/BU1014" (Output Signal = >> uChip0_Cal1_XA1_TA0/N56799) (RLOC=X5Y10, Set=uChip0_Cal1_XA1_TA0/hset) >> FLOP symbol "uChip0_Cal1_XA1_TA0/BU1017" (Output Signal = >> uChip0_Cal1_XA1_TA0/N720) (RLOC=X5Y10, Set=uChip0_Cal1_XA1_TA0/hset) >> The component is already of type "SLICEM". The setting of the >> component type >> is necessary since it is an odd number of columns away from a component >> which >> already has a type of "SLICEM". This second component contains the >> following >> symbols: >> Shift symbol "uChip0_Cal1_XA1_TA0/BU996" (Output Signal = >> uChip0_Cal1_XA1_TA0/N56748) (RLOC=X4Y10, Set=uChip0_Cal1_XA1_TA0/hset) >> FLOP symbol "uChip0_Cal1_XA1_TA0/BU999" (Output Signal = >> uChip0_Cal1_XA1_TA0/N56731) (RLOC=X4Y10, Set=uChip0_Cal1_XA1_TA0/hset) >> Shift symbol "uChip0_Cal1_XA1_TA0/BU1001" (Output Signal = >> uChip0_Cal1_XA1_TA0/N56768) (RLOC=X4Y10, Set=uChip0_Cal1_XA1_TA0/hset) >> FLOP symbol "uChip0_Cal1_XA1_TA0/BU1004" (Output Signal = >> uChip0_Cal1_XA1_TA0/N56430) (RLOC=X4Y10, Set=uChip0_Cal1_XA1_TA0/hset) >> This architecture has two types of components, SLICELs and SLICEMs, in >> alternating columns. Only SLICEMs can contain RAM symbols. >> > >
Reply by ●November 5, 20052005-11-05
"The RPM cannot have shift registers or distributed CLB SelectRAM (single port or dual port) in both odd AND even RLOC columns. The SLICEL has a lookup table that's logic only while the SLICEM has LUTs that can be loaded and read as a single port memory, a dual-port memory, or a shift register." So 1) find all your memory elements, and 2) move them around so they're either all in even RLOC columns or they're all in odd RLOC columns. This will allow all you memory elements to be RLOCed into SLICEM slices. - John_H Andrew Lohbihler wrote:> Thanks John, > > The code did work for a Virtex-II and the details of the packing don't > indicate which column constraint was used. Any idea what constraint should > be changed to make it work in a Virtex-4? There must be a way to tweak the > design for the V4 to make it pack similarily as a V2. Any help will do. > > Thanks, > Andrew > > "John_H" <johnhandwork@mail.com> wrote in message > news:YMQaf.57$Ge6.296@news-west.eli.net... > >>Unlike earlier Virtex family devices, the Virtex-4 has half the slices >>allowed as memory-capable. The RPM cannot have shift registers or >>distributed CLB SelectRAM (single port or dual port) in both odd AND even >>RLOC columns. The SLICEL has a lookup table that's logic only while the >>SLICEM has LUTs that can be loaded and read as a single port memory, a >>dual-port memory, or a shift register. >> >>If the RPM was done for a project in a Virtex-IIPro or older device, >>you'll need to tweak it for the "odd or even column only" constraint of >>the Virtex-4. If your RPM is fresh for this design, simply reconfigure it >>for the constraint you now know is getting in your way. >> >>- John_H
Reply by ●November 6, 20052005-11-06
But why were these changes done ? is it a sacrifice made by Xilinx to allow adding XtremeDSP and other hard cores inside the Virtex-4 ? Or is it simply because a few people use the CLBs as memory or shift registers?
Reply by ●November 6, 20052005-11-06
GaLaKtIkUs� wrote:> But why were these changes done ? is it a sacrifice made by Xilinx to > allow adding XtremeDSP and other hard cores inside the Virtex-4 ? > Or is it simply because a few people use the CLBs as memory or shift > registers? >I'd say it's more because even if you do use the slice as memory & shift egister, it's unlikely that you need ALL of them to be capable of that ... So by only making half of them with this capability, you don't loose much but I'd guess you win quite some space & complexity. Sylvain
Reply by ●November 6, 20052005-11-06
I believe it been said before by Xilinx.. that it was done to reduce the silicon size. Most designers don't use them so its no great loss. And you shouldn't be using RLOCs from an older version silicon with a new version anyway... the mapping is usually done for optimum timings and/or placement... it doesn't automatically follow that what was best for a Vertex 2 is best for a vertex 3 or 4. Simon "Sylvain Munaut" <com.246tNt@tnt> wrote in message news:436db9da$0$20585$ba620e4c@news.skynet.be...> GaLaKtIkUs� wrote: > > But why were these changes done ? is it a sacrifice made by Xilinx to > > allow adding XtremeDSP and other hard cores inside the Virtex-4 ? > > Or is it simply because a few people use the CLBs as memory or shift > > registers? > > > I'd say it's more because even if you do use the slice as memory & shift > egister, it's unlikely that you need ALL of them to be capable of that ... > > So by only making half of them with this capability, you don't loose > much but I'd guess you win quite some space & complexity. > > > Sylvain
Reply by ●November 6, 20052005-11-06
Reply by ●November 6, 20052005-11-06
Either way the reason Xilinx did this does not help someone that is porting this code to a higher Virtex device. They are stuck with this error with no understanding or explanation of how to proceed fixing their code to make it work. This is not good support!! Why can't Xilinx make this clear to engineers upgrading their devices. -Andrew "GaLaKtIkUsT" <taileb.mehdi@gmail.com> wrote in message news:1131255526.842676.30480@g44g2000cwa.googlegroups.com...> But why were these changes done ? is it a sacrifice made by Xilinx to > allow adding XtremeDSP and other hard cores inside the Virtex-4 ? > Or is it simply because a few people use the CLBs as memory or shift > registers? >
