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Why Spartan-3e is the best

Started by Antti Lukats November 5, 2005
Why Spartan-3e is the best
==================
  Antti Lukats
  4.Nov 2005

(I was asked about why I think so in private, but I think
my response could have more general interest so I am posting
the reply to c.a.f.)

-------------------------------------------------------------

At first look there differences between S3 and S3e may not
be so significant however there are several small things
that make Spartan-3e my fist choice (from current low-cost
RAM based FPGA offerings).

1) as Spartan-3 was the first Xilinx silicon on new technology
its kind of logical that Xilinx has fixed in Spartan-3e some
issues related to the use of the new technology. So even if those
are minor, there are still chances that S3e is somewhat better
simply because Xilinx has had more experience with the technology
being used.

2) pricing is promised a little lower, this is not so big deal,
but still, its pretty much logical to prefer silicon with best
price/performance ratio.

3) S3e configuration options are WAY superior over all other RAM
based FPGAs currently in production. S3e is the only FPGA that:

* can load not only from SPI Flash but also from Atmel Dataflash
meaning that a it is the only FPGA around that can directly use
an MMC (Atmel MMC form factor packaged 2/4/8 MByte Dataflash cards)
like Flash card as its main configuration media. So a design with
S3e and MMC Card socket can boot from the removabale flash media
card. Note that the MMC Card socket inserion switch could overide
the 'enable' of the additional on board memory so the SoC loaded
from the inserted into socket Dataflash card could copy a new
bitstream and OS image onto onboard flash, so next 'boot' without
card inserted could come from on board DataFlash. Nice little
feature.

* can load from Parallel Flash, just like the oldies (eg Xilinx first 
FPGA's).
This is VERY good feature as it allows cheap Flash ROMs to be used for both
config and OS image.

* has 'multi boot' option. In Parallel Flash loading mode S3e can
request its own reconfiguration from alternative image.

---

compared to S3, S3e configuration interface allows the use
of SPI or Platform Flash for firmware storage without the
use of extra FPGA IO pin workaround.

S3e configuration is still way less flexible than I could
have designed, but its still the industries best at the moment.


4) S3e has LVDS input onchip termination. I have to admit that
I first found the low cost LVDS onchip termination feature in
Altera Cyclone-II but then I did re-found it in Spartan-3e as
well. It may not so sound like a nig deal, but its a nice
little additional feature that may save some PCB space.

5) Some nice new (compared to other Spartan FPGAs)
package combinations like:
*Largest fabric in VQ100
*Largest fabric in chip-scale package
*Largest fabric in FT256
*Largest fabric in non-BGA package

5) S3e starterkit from Avnet is selling at almost all
time low price of 69USD. (Futre did sell Cyclone kits
for $49 for a while but that kit did not look anything
I would spend money for). To get an eval board with
HS USB chip + FPGA for total cost of $69? Real candy.

6) There are possible some other nice new features
I have not discovered yet :)


Antti Lukats 


Antti Lukats schrieb:

> Why Spartan-3e is the best
> ================== > Antti Lukats > 4.Nov 2005 [snipped Lord's prayer] Amen, Reverend Atti. Is it possible that you are obsessed by S3E?? C'mon, life goes on with and without S3E!! There other things that are important. Even in an engineers life, right? Just my two(euro)cents Falk
"Falk Brunner" <Falk.Brunner@gmx.de> schrieb im Newsbeitrag 
news:3t3o7bFr3hddU1@individual.net...
> Antti Lukats schrieb: > >> Why Spartan-3e is the best > > ================== > > Antti Lukats > > 4.Nov 2005 > > [snipped Lord's prayer] > > Amen, Reverend Atti. > Is it possible that you are obsessed by S3E?? > C'mon, life goes on with and without S3E!! > There other things that are important. Even in an engineers life, right? > > Just my two(euro)cents > Falk
Hi Falk, sure! Like going to movies with the family. "Little Ice-bear II" is on our family menu this afternoon, when Anna (2 years) wakes up from beaty sleep we go. Antti
Antti Lukats wrote:
> 5) Some nice new (compared to other Spartan FPGAs) > package combinations like: > *Largest fabric in VQ100 > *Largest fabric in chip-scale package > *Largest fabric in FT256 > *Largest fabric in non-BGA package
Where did you see that? Looking at http://www.xilinx.com/products/silicon_solutions/fpgas/product_tables.htm#Spartan3E it seems only the two smallest models are available in VQ100 and TQ144 packages. The smallest package for the largest fabric is the FG320, right? The datasheet has the same information. --- Jecel
Jecel wrote:
> Antti Lukats wrote: > >>5) Some nice new (compared to other Spartan FPGAs) >>package combinations like: >>*Largest fabric in VQ100 >>*Largest fabric in chip-scale package >>*Largest fabric in FT256 >>*Largest fabric in non-BGA package > > > Where did you see that? Looking at > http://www.xilinx.com/products/silicon_solutions/fpgas/product_tables.htm#Spartan3E > it seems only the two smallest models are available in VQ100 and TQ144 > packages. The smallest package for the largest fabric is the FG320, > right? The datasheet has the same information.
I think Antti meant that the 3e has the largest resource available in (any) QFP, not that the biggest s3e die goes into a QFP. ie it is more a LUT/package measure. -jg
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag 
news:436edf24$1@clear.net.nz...
> Jecel wrote: >> Antti Lukats wrote: >> >>>5) Some nice new (compared to other Spartan FPGAs) >>>package combinations like: >>>*Largest fabric in VQ100 >>>*Largest fabric in chip-scale package >>>*Largest fabric in FT256 >>>*Largest fabric in non-BGA package >> >> >> Where did you see that? Looking at >> http://www.xilinx.com/products/silicon_solutions/fpgas/product_tables.htm#Spartan3E >> it seems only the two smallest models are available in VQ100 and TQ144 >> packages. The smallest package for the largest fabric is the FG320, >> right? The datasheet has the same information. > > I think Antti meant that the 3e has the largest resource available in > (any) QFP, not that the biggest s3e die goes into a QFP. > ie it is more a LUT/package measure. > > -jg >
yes Jim. also that it has largest fabric in SAME package compared to S3 or other Xilinx FPGA. as example VQ100 is really nice package very thin, so largest LUTs you get in VQ100 is S3e. etc.. worlds largest non BGA FPGA is Actel PA3-3000E I think. Antti
In article <dkmrjm$cg8$1@online.de>, Antti Lukats wrote:
> > as example VQ100 is really nice package very thin, so largest LUTs you get > in VQ100 is S3e. etc..
I realize that there are people out there that need the 1000+ pin packages that large-scale FPGAs offer... but I do wish that 2-5 million "gate" FPGAs would come in VQ100/144 packages. Personally, I'd love to have the capacity, but I really dont need (or want) the complexity and raw bandwidth of having to deal with several hundred (or a thousand) pins... -- [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax
Tobias Weingartner wrote:
> In article <dkmrjm$cg8$1@online.de>, Antti Lukats wrote: >> as example VQ100 is really nice package very thin, so largest LUTs you get >> in VQ100 is S3e. etc.. > > I realize that there are people out there that need the 1000+ pin packages > that large-scale FPGAs offer... but I do wish that 2-5 million "gate" FPGAs > would come in VQ100/144 packages. Personally, I'd love to have the capacity, > but I really dont need (or want) the complexity and raw bandwidth of having > to deal with several hundred (or a thousand) pins...
Just doesn't work that way unfortunately. The large fabric requires a large chip package to contain it. If you were to reduce the number of pin outs, the it would actually require an even larger chip package, as you would now have to add additional multiplexers etc to control the routing to the pins. It would certainly be nice to have the additional logic in a smaller chip, but sorry to say this will only happen with geometry scaling, such as transition to 90nm and possibly to 65nm in the near future.
Bevan Weiss wrote:
> Just doesn't work that way unfortunately. The large fabric requires a > large chip package to contain it. If you were to reduce the number of > pin outs, the it would actually require an even larger chip package, > as you would now have to add additional multiplexers etc to control > the routing to the pins.
No, it wouldn't need any extra multiplexers. They would just not bond out as many of the pads to pins. They already do that to offer several package options for each FPGA. The problem is that you don't save any significant cost by having the same size package with fewer balls or pins. So if the die size requires a package 20mm on a side, it may as well have more than 350 balls, even if some customers don't end up using all of them.
Tobias Weingartner wrote:

>In article <dkmrjm$cg8$1@online.de>, Antti Lukats wrote: > > >>as example VQ100 is really nice package very thin, so largest LUTs you get >>in VQ100 is S3e. etc.. >> >> > >I realize that there are people out there that need the 1000+ pin packages >that large-scale FPGAs offer... but I do wish that 2-5 million "gate" FPGAs >would come in VQ100/144 packages. Personally, I'd love to have the capacity, >but I really dont need (or want) the complexity and raw bandwidth of having >to deal with several hundred (or a thousand) pins... > > >
Unfortunately, the size of the cavity in those small packages is far too small to fit the die for the high density parts, and even if it did fit, you may have power dissipation issues as well. -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759