In Xilinx, how do I delay a signal by a fraction of a clock cycle?

I am outputting a data with a clock 12.5MHz, which will latch the data
into external chip whose input delay is unknown. I am trying to connect
eight FPGA IO pads to the same clock, and delay each of them 1/8 of
my main clock period, i.e. 10 ns, expecting one of them will work correctly.
What constraint can I use in UCF file?

Thanks in advance

"Frank" wrote:

>I am outputting a data with a clock 12.5MHz, which will latch the data
>into external chip whose input delay is unknown. I am trying to connect
>eight FPGA IO pads to the same clock, and delay each of them 1/8 of
>my main clock period, i.e. 10 ns, expecting one of them will work correctly.
>What constraint can I use in UCF file?

Not the right way to solve the problem, as the delay can vary by a lot
depending on part, VCC and temperature.  

For a suggestion of better idea, first, what part?  Second, what other
clocks do you have available?

If you have a 50 MHz clock available, the design can move an output by
10 ns by just changing the clock edge, and by 20 ns by delaying to the
next clock.

A "DCM" might help as well.


-- 
Phil Hays to reply solve: phil_hays at not(coldmail) dot com  
 If not cold then hot

Frank wrote:
> I am outputting a data with a clock 12.5MHz, which will latch the data
> into external chip whose input delay is unknown. I am trying to connect
> eight FPGA IO pads to the same clock, and delay each of them 1/8 of
> my main clock period, i.e. 10 ns, expecting one of them will work correctly.
> What constraint can I use in UCF file?
> 
> Thanks in advance
> 
> 
> 
Hi Frank,
I guess you want to be able to constrain the maximum clock to data delay 
of your FPGA output. If not ignore this message :-)
You can use the OFFSET - OUT - AFTER constraint in the UCF file to do that.
eg. NET "<data_output_pin>" OFFSET = OUT 5 ns AFTER "<Clock_Pin>" HIGH;

Do you have a faster clock available (50 MHz or 100 MHz) ?
Are you sending data to a latch or to an edge-triggered flip-flop or
register?
With a flip-flop or register, just use the opposite clock polarity,
i.e. the clock edge that did NOT generate the output data. That edge is
40 ns later than the data change, and that should be a very safe
margin.
Peter Alfke, Xilinx Applications

"Kunal Shenoy" <kunal.shenoy@xilinx.com> wrote in message
news:dkud96$sp91@cliff.xsj.xilinx.com...
> Frank wrote:
> > I am outputting a data with a clock 12.5MHz, which will latch the data
> > into external chip whose input delay is unknown. I am trying to connect
> > eight FPGA IO pads to the same clock, and delay each of them 1/8 of
> > my main clock period, i.e. 10 ns, expecting one of them will work
correctly.
> > What constraint can I use in UCF file?
> >
> > Thanks in advance
> >
> >
> >
> Hi Frank,
> I guess you want to be able to constrain the maximum clock to data delay
> of your FPGA output. If not ignore this message :-)
> You can use the OFFSET - OUT - AFTER constraint in the UCF file to do
that.
> eg. NET "<data_output_pin>" OFFSET = OUT 5 ns AFTER "<Clock_Pin>" HIGH;

Thank you, I used to think OFFSET gives a maximum delay, which means an
offset value of 60ns
or 70ns gives same result, since the real offset is 50ns. Am I right?
I will try out this OFFSET technique.

Just wanna make sure we are talking about the same thing.
Your situation:
You have an FPGA and another device being clocked by the same signal.
The FPGA outputs some data to the external device.
On active clock edge 1 (for example), the FPGA will output some data.
The external device will register that data (as input) on active clock
edge 2. Now you want to be able to satisfy the setup time of the
external device's input flip flop, which means you want to be able to
specify the MAXIMUM delay from the 1st active clock edge to the FPGA
data being output. That can be done using the OFFSET-OUT-AFTER
constraint in the UCF. It will take into account not only the delay of
the data but also of the clock that activates the output flip flop.

Kunal @ Xilinx

Frank schrieb:
> I am outputting a data with a clock 12.5MHz, which will latch the data
> into external chip whose input delay is unknown. I am trying to connect
> eight FPGA IO pads to the same clock, and delay each of them 1/8 of
> my main clock period, i.e. 10 ns, expecting one of them will work correctly.
> What constraint can I use in UCF file?
> 
> Thanks in advance
> 
> 
> 
Hi Frank,
I would recommend you to use or generate somehow a higher Clock 
frequency. 50MHz would be just fine. Unfortunately you may be unable to 
generate this Clock from your 12.5 MHz with the builtin DLLs/DCMs for 
these require some minimum frequency (see the datasheets for details).

So, when I assume for a moment that you have a 50 MHZ Clock available 
you can build two cyclic shiftregister that shifts a single '1' over 4 
FFs. One must be clocked by the rising edge one by the falling edge of 
the 50 MHz. Then you can use these 8 outputs as clock enable signals for 
your output FFs which also have to use rising and falling edge clocks 
alternating from one FF to the next.

A 12.5MHz Clock for the rest of your design can be derived from that 50 
MHz easily by the DLLs/DCMs and your output value can be stored in an 
internal register that feeds the IOB-FFs which take the values with 
their respective delays due to the generated CE-Signals.

Thus the design wil be totally synchronous, and the Output to PAD delays 
of the IOBs should be quite equal anyway.

have a nice synthesis
   Eilert

Frank schrieb:
> I am outputting a data with a clock 12.5MHz, which will latch the data
> into external chip whose input delay is unknown. 
Other posters helped you with your suggested approach. But I doubt that
what you are trying to do is neccessary.

Whtat do you men by input delay? If data is clocked into a device
usually there are two important parameters: Setup and hold time.
It should be possible to find out what these are for your device. If you
give us a part number maybe someone even knows the values.

Also, for virtually all devices that I know of both parameters are an
order of magnitude smaller than 40ns. Therefore if you register the data
at the opposite edge of your clock you are very likely meeting both
requirements.

Also, hold times tend to be very small. Probably smaller than the Tco
parameter of the FPGA. If this is true you can achieve a simpler design
by registering the data with the same clock edge for both devices.

Kolja Sulimma

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Frank schrieb:
> I am outputting a data with a clock 12.5MHz, which will latch the data
> into external chip whose input delay is unknown. 
Other posters helped you with your suggested approach. But I doubt that
what you are trying to do is neccessary.

Whtat do you men by input delay? If data is clocked into a device
usually there are two important parameters: Setup and hold time.
It should be possible to find out what these are for your device. If you
give us a part number maybe someone even knows the values.

Also, for virtually all devices that I know of both parameters are an
order of magnitude smaller than 40ns. Therefore if you register the data
at the opposite edge of your clock you are very likely meeting both
requirements.

Also, hold times tend to be very small. Probably smaller than the Tco
parameter of the FPGA. If this is true you can achieve a simpler design
by registering the data with the same clock edge for both devices.

Kolja Sulimma

"backhoes" <nix@nirgends.xyz> wrote in message 
news:dkur6u$jgj$1@hermes1.rz.hs-bremen.de...
> Hi Frank,
> I would recommend you to use or generate somehow a higher Clock frequency. 
> 50MHz would be just fine. Unfortunately you may be unable to generate this 
> Clock from your 12.5 MHz with the builtin DLLs/DCMs for these require some 
> minimum frequency (see the datasheets for details).
>
Eilert,
You can use the DCMs with clock inputs down to 1MHz as long as you use 
"frequency synthesis" mode, i.e. use the CLKFX output(s). The output clock 
must be greater than 24 MHz. I'm using the "datasheets for details"! ;-)
Cheers then, Syms.