Can't pack into OLOGIC

Hi,

It's a few days since I can't put a FF into IOB register:

XST (7.1.4) option: -equivalent register removal: NO -pack IO registers into IOB : YES

MAP (7.1.4) option: -pack IO registers into IOB : For inputs and outputs

moreover I applied the attribute on the name of the clocked process that represents the FF: attribute IOB of iob_t : label is "TRUE";

It is for a bidirectionnal signal: input is registered into IOB, output is also registered there, but the duplicated tristate_enable registers don't want to go inside the OLOGIC (Virtex 4). Each of them is not that far, but not into the IOB!

Any suggestion?

John,
can you please post the MAP error message?
Thanks,
Aurash

john wrote:

>Hi,
>
>It's a few days since I can't put a FF into IOB register:
>
>XST (7.1.4) option: -equivalent register removal: NO -pack IO registers into IOB : YES
>
>MAP (7.1.4) option: -pack IO registers into IOB : For inputs and outputs
>
>moreover I applied the attribute on the name of the clocked process that represents the FF: attribute IOB of iob_t : label is "TRUE";
>
>It is for a bidirectionnal signal: input is registered into IOB, output is also registered there, but the duplicated tristate_enable registers don't want to go inside the OLOGIC (Virtex 4). Each of them is not that far, but not into the IOB!
>
>Any suggestion?
>  
>


-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     

john wrote:

> It is for a bidirectionnal signal: input is registered into IOB, output is also registered there, but the duplicated tristate_enable registers don't want to go inside the OLOGIC (Virtex 4). Each of them is not that far, but not into the IOB!
>

- Make sure the tristate 'registers' are duplicated, not the output of
the tristate register.
- Make sure the duplicated registers have proper attribute so the
synthesis tool doesn't optimize them into a single register.

You may have already done what I mentioned.  One more
- make sure the tristate registers feed nothing else outside of the
IOB.

You might want to post your code if it still doesn't do it...

the

I don't have any error: I just checked with fpga_editor that I am not using both FF inside the OLOGIC.

This results in a poor timing because the routing adds to the iobuf timing

thanks for help.

I respect these three conditions. (I checked with fpgaeditor)

code is (removed reset as in teXclusive on xilinx website):



iob_t:process(CLK) begin if rising_edge(CLK) then DATA_REG(i) <= DATA(i); tristate_enable_reg(i) <= tristate_enable_reg(i); end if; end process;

well maybe I'll consider opening a webcase!

John,

tristate_enable_reg(i) <= tristate_enable_reg(i);  ??

Is that what you wanted?

Syms

"john" <john.wo.71@gmail.com> wrote in message 
news:ee91b0b.5@webx.sUN8CHnE...
> thanks for help.
>
> I respect these three conditions. (I checked with fpgaeditor)
>
> code is (removed reset as in teXclusive on xilinx website):
>
>
>
> iob_t:process(CLK) begin if rising_edge(CLK) then DATA_REG(i) <= DATA(i); 
> tristate_enable_reg(i) <= tristate_enable_reg(i); end if; end process;
>
> well maybe I'll consider opening a webcase! 

sorry I mistyped!

obviously it is: tristate_enable_reg(i) <= tristate_enable(i);

john wrote:
> the

You might want to try:

attribute equivalent_register_removal of tristate_enable_reg: signal is 
"no";

---
Joe