Stupid reset question

Hello,

I'm in the final phase of a design in VHDL on a Cyclon, and i am
really puzzled by something. 
I do not have an external reset pin, so how can i ensure that my
states machines start at the right state, that all values are well
initialized and everything ?

It seems to work as it is now, but i couldn't find any litterature on
this subject.

Many thanks
Nick

Nick,

I assume that Cyclone works similarly to our own FPGAs in that all flip 
flops are inti tally set to 0 by the house-cleaning (initialization 
prior to configuration) at power on.

You can check this by reading their manual on what happens during power 
on and configuration.

Then, during configuration, the state of the flip flops for logic may 
(or may not) be set, or reset to a state as specified by the bitstream 
(depends on the device, and its options when being configured).

If you have designed the state machine with no hidden states, and in 
such a way that it will always return to a known state given a set of 
good inputs, there is no need for a reset.

In the case of a 1-hot state machine (very popular in FPGAs) this also 
means that detection of having more than one state set (more than one 
flip flop) must decode and send you back to a known state of having only 
one state active!

Austin

Nick wrote:

> Hello,
> 
> I'm in the final phase of a design in VHDL on a Cyclon, and i am
> really puzzled by something. 
> I do not have an external reset pin, so how can i ensure that my
> states machines start at the right state, that all values are well
> initialized and everything ?
> 
> It seems to work as it is now, but i couldn't find any litterature on
> this subject.
> 
> Many thanks
> Nick

Thank you Austin.
I'll check the documentation and secure the state machines.

Regards,
Nick


On Tue, 22 Nov 2005 15:55:00 -0800, Austin Lesea <austin@xilinx.com>
wrote:

>Nick,
>
>I assume that Cyclone works similarly to our own FPGAs in that all flip 
>flops are inti tally set to 0 by the house-cleaning (initialization 
>prior to configuration) at power on.
>
>You can check this by reading their manual on what happens during power 
>on and configuration.
>
>Then, during configuration, the state of the flip flops for logic may 
>(or may not) be set, or reset to a state as specified by the bitstream 
>(depends on the device, and its options when being configured).
>
>If you have designed the state machine with no hidden states, and in 
>such a way that it will always return to a known state given a set of 
>good inputs, there is no need for a reset.
>
>In the case of a 1-hot state machine (very popular in FPGAs) this also 
>means that detection of having more than one state set (more than one 
>flip flop) must decode and send you back to a known state of having only 
>one state active!
>
>Austin
>
>Nick wrote:
>
>> Hello,
>> 
>> I'm in the final phase of a design in VHDL on a Cyclon, and i am
>> really puzzled by something. 
>> I do not have an external reset pin, so how can i ensure that my
>> states machines start at the right state, that all values are well
>> initialized and everything ?
>> 
>> It seems to work as it is now, but i couldn't find any litterature on
>> this subject.
>> 
>> Many thanks
>> Nick

Nick <nick@no-domain> wrote:

>I'm in the final phase of a design in VHDL on a Cyclon, and i am
>really puzzled by something. 
>I do not have an external reset pin, so how can i ensure that my
>states machines start at the right state, that all values are well
>initialized and everything ?

I've never used Cyclon, but I'd expect that there is an asynchronous
reset and/or set applied as part of configuration.  If so, then what
you need to worry about is the first clock.  As the reset will be
released at different times across the chip, some FFs may be released
from reset before others, and a statemachine may end up in a non valid
state that will prevent correct functioning.  This can be solved by
using safe statemachines, so that all non-valid states map into valid
states in at most a few clocks, or by using statemachines with no
invalid states at all.  A binary counter, for example, has only valid
states.

Now, suppose there was a "reset" statemachine that held reset to the
rest of the statemachines until the configuration was released and
all?

This is fairly simple, put in a binary counter or similar safe
statemachine with more than enough counts (or states) to make sure
that the reset is released, have it hold synchronous reset to the
reset of the design until count complete, then release it.  Example in
VHDL follows:


use ieee.numeric_std.all;
entity
...
architecture
...
  Signal reset :   std_logic := '1';
  Signal count :   unsigned(3 downto 0) := "0000";
begin
  --
  -- This counter is used to hold all statemachines in reset for the
  -- first 8 or so clocks after the end of configuration.
  -- 
  RESET_STATE: process(clk)
  begin
    if rising_edge(clk) then
       reset <= count(3);
       if count(3) = '1' then
         count <= count + 1;
       end if;
    end if;
  end process;
(rest of code)


Note that not all synthesis tools can correctly handle this.  Some of
the old tools would have problems with this.  While I've used similar
tricks in the past, I have not verified this exact code.

Note that the number of bits in count needs to be large enough to get
well past the end of asynchronous reset, and not so large as to cause
startup delays.


-- 
Phil Hays to reply solve: phil_hays at not(coldmail) dot com  
 If not cold then hot

When Quartus runs it prints a little message that all flip-flops that have a
reset high.. will be high after initialisation.. or words to that effect.

Simon

"Austin Lesea" <austin@xilinx.com> wrote in message
news:dm0b4s$4g56@xco-news.xilinx.com...
> Nick,
>
> I assume that Cyclone works similarly to our own FPGAs in that all flip
> flops are inti tally set to 0 by the house-cleaning (initialization
> prior to configuration) at power on.
>
> You can check this by reading their manual on what happens during power
> on and configuration.
>
> Then, during configuration, the state of the flip flops for logic may
> (or may not) be set, or reset to a state as specified by the bitstream
> (depends on the device, and its options when being configured).
>
> If you have designed the state machine with no hidden states, and in
> such a way that it will always return to a known state given a set of
> good inputs, there is no need for a reset.
>
> In the case of a 1-hot state machine (very popular in FPGAs) this also
> means that detection of having more than one state set (more than one
> flip flop) must decode and send you back to a known state of having only
> one state active!
>
> Austin
>
> Nick wrote:
>
> > Hello,
> >
> > I'm in the final phase of a design in VHDL on a Cyclon, and i am
> > really puzzled by something.
> > I do not have an external reset pin, so how can i ensure that my
> > states machines start at the right state, that all values are well
> > initialized and everything ?
> >
> > It seems to work as it is now, but i couldn't find any litterature on
> > this subject.
> >
> > Many thanks
> > Nick

Nick wrote:
> Hello,
> 
> I'm in the final phase of a design in VHDL on a Cyclon, and i am
> really puzzled by something. 
> I do not have an external reset pin, so how can i ensure that my
> states machines start at the right state, that all values are well
> initialized and everything ?
> 
> It seems to work as it is now, but i couldn't find any litterature on
> this subject.
> 
> Many thanks
> Nick


Nick,

I don't know about Cyclone FPGAs but I suppose that they have some sort 
of digital clock manager, DCM, as the Xilnx FPGAs have. In some designs 
I have used the inverse of the DCM lock signal as global reset signal. 
In that way all flip-flops in the design are reset simultaneously when 
the clock is stable. (The DCM lock signal is asserted when all outputs 
from the component are locked).

I don't know if this is considered good or bad practise, but it is 
working quite good. Hasn't failed yet.

-- 
-----------------------------------------------
Johan Bernsp�ng, xjohbex@xfoix.se
Research engineer

Swedish Defence Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems

www.foi.se

Please remove the x's in the email address if
replying to me personally.
-----------------------------------------------

Phil Hays wrote:
> Nick <nick@no-domain> wrote:
<snipped>
> use ieee.numeric_std.all;
> entity
> ...
> architecture
> ...
>   Signal reset :   std_logic := '1';
>   Signal count :   unsigned(3 downto 0) := "0000";
> begin
>   --
>   -- This counter is used to hold all statemachines in reset for the
>   -- first 8 or so clocks after the end of configuration.
>   --
>   RESET_STATE: process(clk)
>   begin
>     if rising_edge(clk) then
>        reset <= count(3);
>        if count(3) = '1' then
>          count <= count + 1;
>        end if;
>     end if;
>   end process;
> (rest of code)
>
>
> Note that not all synthesis tools can correctly handle this.  Some of
> the old tools would have problems with this.  While I've used similar
> tricks in the past, I have not verified this exact code.
>
> Note that the number of bits in count needs to be large enough to get
> well past the end of asynchronous reset, and not so large as to cause
> startup delays.
>
>
> --
> Phil Hays to reply solve: phil_hays at not(coldmail) dot com
>  If not cold then hot

Shouldn't:
        if count(3) = '1' then
          count <= count + 1;
be:
        if count(3) = '0' then
          count <= count + 1;

-Dave Pollum

"Dave Pollum" wrote:

>Shouldn't:
>        if count(3) = '1' then
>          count <= count + 1;
>be:
>        if count(3) = '0' then
>          count <= count + 1;

Yes.  Thank you.


-- 
Phil Hays to reply solve: phil_hays at not(coldmail) dot com  
 If not cold then hot

Very interresting solution. I buy it.

Nick

On Tue, 22 Nov 2005 22:51:04 -0800, Phil Hays
<Spampostmaster@comcast.net> wrote:

>Nick <nick@no-domain> wrote:
>
>>I'm in the final phase of a design in VHDL on a Cyclon, and i am
>>really puzzled by something. 
>>I do not have an external reset pin, so how can i ensure that my
>>states machines start at the right state, that all values are well
>>initialized and everything ?
>
>I've never used Cyclon, but I'd expect that there is an asynchronous
>reset and/or set applied as part of configuration.  If so, then what
>you need to worry about is the first clock.  As the reset will be
>released at different times across the chip, some FFs may be released
>from reset before others, and a statemachine may end up in a non valid
>state that will prevent correct functioning.  This can be solved by
>using safe statemachines, so that all non-valid states map into valid
>states in at most a few clocks, or by using statemachines with no
>invalid states at all.  A binary counter, for example, has only valid
>states.
>
>Now, suppose there was a "reset" statemachine that held reset to the
>rest of the statemachines until the configuration was released and
>all?
>
>This is fairly simple, put in a binary counter or similar safe
>statemachine with more than enough counts (or states) to make sure
>that the reset is released, have it hold synchronous reset to the
>reset of the design until count complete, then release it.  Example in
>VHDL follows:
>
>
>use ieee.numeric_std.all;
>entity
>...
>architecture
>...
>  Signal reset :   std_logic := '1';
>  Signal count :   unsigned(3 downto 0) := "0000";
>begin
>  --
>  -- This counter is used to hold all statemachines in reset for the
>  -- first 8 or so clocks after the end of configuration.
>  -- 
>  RESET_STATE: process(clk)
>  begin
>    if rising_edge(clk) then
>       reset <= count(3);
>       if count(3) = '1' then
>         count <= count + 1;
>       end if;
>    end if;
>  end process;
>(rest of code)
>
>
>Note that not all synthesis tools can correctly handle this.  Some of
>the old tools would have problems with this.  While I've used similar
>tricks in the past, I have not verified this exact code.
>
>Note that the number of bits in count needs to be large enough to get
>well past the end of asynchronous reset, and not so large as to cause
>startup delays.

Phil Hays wrote:

> This is fairly simple, put in a binary counter or similar safe
> statemachine with more than enough counts (or states) to make sure
> that the reset is released, have it hold synchronous reset to the
> reset of the design until count complete, then release it.  Example in
> VHDL follows:
> 
> 
> use ieee.numeric_std.all;
> entity
> ...
> architecture
> ...
>   Signal reset :   std_logic := '1';
>   Signal count :   unsigned(3 downto 0) := "0000";
> begin
>   --
>   -- This counter is used to hold all statemachines in reset for the
>   -- first 8 or so clocks after the end of configuration.
>   -- 
>   RESET_STATE: process(clk)
>   begin
>     if rising_edge(clk) then
>        reset <= count(3);
>        if count(3) = '1' then
>          count <= count + 1;
>        end if;
>     end if;
>   end process;
> (rest of code)
> 
> 

This is not safe as presented, as you can't guarantee all the flip-flops 
in the counter will be released from reset on the same clock cycle.  To 
make this robust, the power up reset has to be registered by clk and 
that local synchronous reset used to reset the counter.  In Xilinx 
FPGAs, it is easier and more compact to use the SRL16 as a shift 
register to delay the reset, and it avoids the reset signal time of 
arrival issue inside the reset circuit.