Hello, Is there an existing flow for simulating PLB DDR in ModelSim using EDK 7.1 SP2 in a full system (PPCs, pcores,etc)? The instructions are being stored in BRAMs, as to avoid DDR initialization hassles. I have been simulating the data-only DDR using BRAMs, however, to get a more accurate depiction of the system, I would like to use DDR in simulation. Thanks, NN
Simulating PLB DDR in EDK 7.1 SP2 using ModelSim 6.0a
Started by ●November 23, 2005
Reply by ●November 23, 20052005-11-23
Nju Njoroge wrote:> Hello, > > Is there an existing flow for simulating PLB DDR in ModelSim using EDK > 7.1 SP2 in a full system (PPCs, pcores,etc)? The instructions are being > stored in BRAMs, as to avoid DDR initialization hassles. I have been > simulating the data-only DDR using BRAMs, however, to get a more > accurate depiction of the system, I would like to use DDR in > simulation.Sure you can simulate that. Do you have the DDR memory simulation models? If not, Micron provides good models on their web site for the individual chips. Other than that, a specific question of what it is you are having trouble with would help; your question is too vague to me (or maybe I am overlooking something).
Reply by ●November 24, 20052005-11-24
Duane Clark wrote:> Nju Njoroge wrote: > > Hello, > > > > Is there an existing flow for simulating PLB DDR in ModelSim using EDK > > 7.1 SP2 in a full system (PPCs, pcores,etc)? The instructions are being > > stored in BRAMs, as to avoid DDR initialization hassles. I have been > > simulating the data-only DDR using BRAMs, however, to get a more > > accurate depiction of the system, I would like to use DDR in > > simulation. > > Sure you can simulate that. Do you have the DDR memory simulation > models? If not, Micron provides good models on their web site for the > individual chips. Other than that, a specific question of what it is you > are having trouble with would help; your question is too vague to me (or > maybe I am overlooking something).Thanks for the pointers. I'm trying to observe how my design interacts with the PLB DDR Controller in simulation, but to do so, there needs to be a DDR model with which the PLB DDR Controller can interface in simulation. My design has a master PLB interface that issues writes and reads to the PLB DDR controller. Previously, I have been using a PLB BRAM controller, which I verified works in both simulation and in hardware. However, I have been observing differences when I replace the PLB BRAM controller with the DDR. Specifically, for certain test cases, the design using the DDR controller doesn't work. Since my design interacts with the PLB bus, I did not change it when I switched over from the BRAM controller to the DDR controller.