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Re: Why does two channels of ADC give different outputs?

Started by Jerry Avins November 29, 2005
Frank wrote:
> I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218). > When I connect I channel from DAC to I & Q channel of ADC, I am seeing > vastly > different digital outputs on ADC (sampling three pins on oscilloscope). What > might > be the cause?
Analog offset and gain difference is most likely. Nonlinearity is possible. Could a hold capacitor be defective? Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218).
When I connect I channel from DAC to I & Q channel of ADC, I am seeing
vastly
different digital outputs on ADC (sampling three pins on oscilloscope). What
might
be the cause?



"Jerry Avins" <jya@ieee.org> wrote in message
news:zJudne6ssMf6SxbeRVn-vg@rcn.net...
> Frank wrote: > > I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog
AD9218).
> > When I connect I channel from DAC to I & Q channel of ADC, I am seeing > > vastly > > different digital outputs on ADC (sampling three pins on oscilloscope).
What
> > might > > be the cause? > > Analog offset and gain difference is most likely. Nonlinearity is > possible. Could a hold capacitor be defective? > > Jerry > -- > Engineering is the art of making what you want from things you can get. > &#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;
OMG! There are 3 ADC boards in my lab, all of them had been badly tampered and the one I am using is the least tampered piece. Maybe I am really doomed. :-(
Frank schrieb:
> I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218). > When I connect I channel from DAC to I & Q channel of ADC, I am seeing > vastly > different digital outputs on ADC (sampling three pins on oscilloscope). What > might > be the cause?
You will never, ever, get a noiseless analog signal. Do you know how signed binary numbers work? Are you aware, that there are pairs of numbers that are very close together, but have all or many different bits? In your case noise of less than 1mV can change the ADC value from -1 to 0. This will flip all bits. Therefore you probably have no problem at all. But you will need to look at all bits, not just 4. But you could start with looking at the 4 higher bits, this will give you results acurate to 1/16 of a Volt. Please note that asking essentially the same question three times is considered inpolite in usenet. Like shouting around in class. Also, most of the newsgroups you posted to are completely unrelated to your problem. You did not even mention FPGAs yet. Kolja Sulimma
"Kolja Sulimma" <news@sulimma.de> wrote in message
news:438c0e6e$0$27886$9b4e6d93@newsread4.arcor-online.net...
> Frank schrieb: > > I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog
AD9218).
> > When I connect I channel from DAC to I & Q channel of ADC, I am seeing > > vastly > > different digital outputs on ADC (sampling three pins on oscilloscope).
What
> > might > > be the cause? > > You will never, ever, get a noiseless analog signal. > Do you know how signed binary numbers work? > Are you aware, that there are pairs of numbers that are very close > together, but have all or many different bits? > In your case noise of less than 1mV can change the ADC value from -1 to > 0. This will flip all bits. > > Therefore you probably have no problem at all. But you will need to look > at all bits, not just 4. But you could start with looking at the 4 > higher bits, this will give you results acurate to 1/16 of a Volt. > > Please note that asking essentially the same question three times is > considered inpolite in usenet. Like shouting around in class. Also, > most of the newsgroups you posted to are completely unrelated to your > problem. You did not even mention FPGAs yet. > > Kolja Sulimma
Yeah you are right. I have a Virtex 2 FPGA, and I am doing some signal processing with it. Now I am borrowing a logic analyzer and hope that will help me do the measurement better. Thank you for the noise and here is another question: Now I set NFS/GAIN = 0 on datasheet it says "offset binary output available, 1 V p-p supported;". and ADC input is -20mV ~ 0.8V, what range of digital values do I get after ADC? What does that offset mean here? Is this interpretation correct? 0 for -20mV, 0xCCC for 0.8V?
Frank schrieb:
> Yeah you are right. I have a Virtex 2 FPGA, and I am doing some signal > processing > with it. Now I am borrowing a logic analyzer and hope that will help me do > the measurement better.
Use Chipscope ILA. Your university has a site license or at least can get one for free from XUP.
> Now I set NFS/GAIN = 0 on datasheet it says "offset binary output available, > 1 V p-p supported;". > and ADC input is -20mV ~ 0.8V, what range of digital values do I get after > ADC? What does that > offset mean here? > > Is this interpretation correct? > 0 for -20mV, > 0xCCC for 0.8V?
Offset binary output means that a fixed value is added to the output to avoid negative numbers for negative input voltages (Whatever negative means for you ADC). The analog 0 voltage and the digital offset added to the measurement should be presented in the datasheet. Kolja Sulimma
Frank wrote:

   ...

> Now I set NFS/GAIN = 0 on datasheet it says "offset binary output available, > 1 V p-p supported;". > and ADC input is -20mV ~ 0.8V, what range of digital values do I get after > ADC? What does that > offset mean here? > > Is this interpretation correct? > 0 for -20mV, > 0xCCC for 0.8V?
Why 0xCCC? for 12 bits, you should get 0xFFF. Jerry -- Engineering is the art of making what you want from things you can get. &#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;
"Frank" <Francis.invalid@hotmail.com> wrote in message
news:438bd5a3$1@news.starhub.net.sg...
> I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218). > When I connect I channel from DAC to I & Q channel of ADC, I am seeing > vastly > different digital outputs on ADC (sampling three pins on oscilloscope).
What
> might > be the cause? > > >
When using logic analyzer to sample ADC outputs, i am getting strange outputs. Right channel, bit 9,8,7,6 stick to 1, bit 0 stick to zero, while bits 5,4,3,2,1 varies during active, while sticking to 1 during idle mode. Left channel, bit 7,5 stick to 0, bit 9,4 switches during active, stick to 1 in idle mode, bit 8,6,3,2 switches during active, stick to 0 during idle (I expect 9:2 of both channel to behave in this manner), bit 1:0 are switching during idle and active (noise during idle mode). I double checked my settings, but found nothing wrong. How can I proceed now?
"Frank" <Francis.invalid@hotmail.com> wrote in message
news:438d4a78$1@news.starhub.net.sg...
> When using logic analyzer to sample ADC outputs, i am getting strange > outputs. > > Right channel, > bit 9,8,7,6 stick to 1, bit 0 stick to zero, while bits 5,4,3,2,1 varies > during active, while sticking to > 1 during idle mode. > > Left channel, > bit 7,5 stick to 0, bit 9,4 switches during active, stick to 1 in idle
mode,
> bit 8,6,3,2 switches during > active, stick to 0 during idle (I expect 9:2 of both channel to behave in > this manner), bit 1:0 are > switching during idle and active (noise during idle mode).
Do you use any bus control signal (RD in combination with CE for the ADC for example) to trigger the logic analyser? If not, you are just measuring all bus activity, not just the output from the ADC. Meindert
"Meindert Sprang" <mhsprang@NOcustomSPAMware.nl> wrote in message
news:11oqj75td1vni04@corp.supernews.com...
> "Frank" <Francis.invalid@hotmail.com> wrote in message > news:438d4a78$1@news.starhub.net.sg... > > When using logic analyzer to sample ADC outputs, i am getting strange > > outputs. > > > > Right channel, > > bit 9,8,7,6 stick to 1, bit 0 stick to zero, while bits 5,4,3,2,1 varies > > during active, while sticking to > > 1 during idle mode. > > > > Left channel, > > bit 7,5 stick to 0, bit 9,4 switches during active, stick to 1 in idle > mode, > > bit 8,6,3,2 switches during > > active, stick to 0 during idle (I expect 9:2 of both channel to behave
in
> > this manner), bit 1:0 are > > switching during idle and active (noise during idle mode). > > Do you use any bus control signal (RD in combination with CE for the ADC
for
> example) to trigger the logic analyser? If not, you are just measuring
all
> bus activity, not just the output from the ADC. > > Meindert > >
In my digital side, I have a PHY_EN pin which is high when the digital circuit repetitively sends out same data, and the digital circuits work for 30us and idle for 10us. On logic analyzer, I set the LA to start filling in the internal memory (256K) once PHY_EN is high, thus I can capture 20 repetitions. I am sure the data capture is correct.