Slow FIFO using external SRAM

I need to implement slow FIFO (16-bit wide, max. 10 MHz) using external 
single-port SRAM connected to the FPGA (Spartan II/III).

Does anyone have similar FIFO controller (sync/async) implemented using 
VHDL?

Thanks,

Damir

damir wrote:
> I need to implement slow FIFO (16-bit wide, max. 10 MHz) using external
> single-port SRAM connected to the FPGA (Spartan II/III).
>
> Does anyone have similar FIFO controller (sync/async) implemented using
> VHDL?

A FIFO in a single-port RAM?  Neat trick, although I suppose the slow
speed makes it do-able.

-a

I would design a reasonably fast state machine ( 50 MHz?) that keeps
track of the read and write requests, updates the two addresses and
multiplexes them appropriately to the external SRAM. If read-access
time is important, you could always pre-fetch the next entry and store
it in an on-chip register. The state machine must check for the two
addresses becoming equal. If read causes them to become equal, the FIFO
is empty, if write causes it, the FIFO is full.
The slow speed makes all this possible, and even easy.
Don't worry too much about metastability of the control circuitry. Just
make sure that there is an extra 5 ns of settling-time slack available.
Peter Alfke, Xilinx Applications

Thanks for the hint, I'll try this approach!

Damir

"Peter Alfke" <peter@xilinx.com> wrote in message 
news:1133292476.312758.278240@f14g2000cwb.googlegroups.com...
>I would design a reasonably fast state machine ( 50 MHz?) that keeps
> track of the read and write requests, updates the two addresses and
> multiplexes them appropriately to the external SRAM. If read-access
> time is important, you could always pre-fetch the next entry and store
> it in an on-chip register. The state machine must check for the two
> addresses becoming equal. If read causes them to become equal, the FIFO
> is empty, if write causes it, the FIFO is full.
> The slow speed makes all this possible, and even easy.
> Don't worry too much about metastability of the control circuitry. Just
> make sure that there is an extra 5 ns of settling-time slack available.
> Peter Alfke, Xilinx Applications
> 

damir wrote:
> I need to implement slow FIFO (16-bit wide, max. 10 MHz) using external
> single-port SRAM connected to the FPGA (Spartan II/III).
>
> Does anyone have similar FIFO controller (sync/async) implemented using
> VHDL?
>
> Thanks,
>
> Damir

I would put two small FIFOs on the FPGA, and then have a simple,
synchronous state machine to control the external RAM. The state
machine would look at how full/empty the FIFOs are, and based on their
priority determine whether it will do a either a read or write access
to the external RAM.

If you need an asych FIFO, then use one of the on-chip FIFOs to cross
the clock domains, and keep the rest on the same clock.

Andy Peters wrote:
> damir wrote:
> 
>>I need to implement slow FIFO (16-bit wide, max. 10 MHz) using external
>>single-port SRAM connected to the FPGA (Spartan II/III).
>>
>>Does anyone have similar FIFO controller (sync/async) implemented using
>>VHDL?
> 
> 
> A FIFO in a single-port RAM?  Neat trick, although I suppose the slow
> speed makes it do-able.

  Most Video systems are essentially FIFOs - the simplest ones just 
alternate R/W slots, at 2x the bandwidth - with the caveats that most of 
the available WRITE slots are ignored, and the READ slots will pause 
during non-display time zones.
  To ease the EMC, the WRITE slot should activate the WR address only
when actually needed.
  Normally, what needs the most attention is the WR_Enable pulse
setup and hold times, so that becomes narrower than the 1/2 time slot (50ns)
  Peter's idea of 50MHz state engine, would allow you to allocate
2 tw to read, and 3 tw to write, with a centred 20ns WRN pulse width,
using simple sync designs - or you could go to 60MHz and do 3tw+3tw,
- decreases tWRN to 16.6ns, but increases tRdCYC to 50ns.....

-jg

Andy Peters wrote:

> 
> A FIFO in a single-port RAM?  Neat trick, although I suppose the slow
> speed makes it do-able.
> 
> -a
> 
Andy,

Sure, I've done that many times, as well as virtual multi-port memory. 
The key is to time multiplex the ports into the single port using a 
faster memory clock than the access rate you need on any one port.

Damir,
It isn't really a hard problem, you basically have two address counters 
muxed into the single address of the RAM.  An additional up/down counter 
will give you the population count needed for a synchronous FIFO, and a 
little bit of extra logic to decode the flags from the population count 
is all that it takes.  An async FIFO can only be approximated by a 
single ported memory, because by definition all accesses to the memory 
happen on the same clock domain.  For an 'async' fifo you will need to 
implement a syncrhonous fifo in the memory with a small on-chip async 
fifo cascaded to the input or output to take care of the clock domain 
crossing.

Ray Andraka wrote:
> Andy Peters wrote:
>
> >
> > A FIFO in a single-port RAM?  Neat trick, although I suppose the slow
> > speed makes it do-able.
> >
> > -a
> >
> Andy,
>
> Sure, I've done that many times, as well as virtual multi-port memory.
> The key is to time multiplex the ports into the single port using a
> faster memory clock than the access rate you need on any one port.

OK, of course you're right :)  I wasn't thinkin'.

I built an audio digital delay out of a CPLD, an audio CODEC (DAC and
ADC in the same chip) and a couple of async SRAMs.  Basically, it's a
big FIFO. Two address pointers are maintained, one for read, one for
write.  Empty and full flags are irrelevant.  A state machine, running
at the CODEC MCLK frequency,  handles interleaving the memory reads and
writes.  It's pretty neat.  A microcontroller handles the interface to
an LCD and a rotary encoder.

It'd be a good homework assignment for a VHDL or Verilog class.

-a

Nice solution!

"Arlet" <usenet+5@ladybug.xs4all.nl> wrote in message 
news:1133294098.430743.59950@g14g2000cwa.googlegroups.com...
> damir wrote:
>> I need to implement slow FIFO (16-bit wide, max. 10 MHz) using external
>> single-port SRAM connected to the FPGA (Spartan II/III).
>>
>> Does anyone have similar FIFO controller (sync/async) implemented using
>> VHDL?
>>
>> Thanks,
>>
>> Damir
>
> I would put two small FIFOs on the FPGA, and then have a simple,
> synchronous state machine to control the external RAM. The state
> machine would look at how full/empty the FIFOs are, and based on their
> priority determine whether it will do a either a read or write access
> to the external RAM.
>
> If you need an asych FIFO, then use one of the on-chip FIFOs to cross
> the clock domains, and keep the rest on the same clock.
> 

Peter's explanation on how to implement a FIFO cannot be
improved much, if any - this is how FIFOs are implemented
in hard- and software.
Here is an alternative to building your own FIFO out
of RAM - has worked for me more than once.
If the purpose is to have the FIFO (and not to build it, say,
for learning or economic purposes), you can use one of
the 72XX (IDT used to make them) FIFO chips. They have
the R/W pointer circuitry inside etc., really convenient
to use - and you will need no memory address lines out
of the FPGA, nor will the data necessarily go through it
(that is, you can just handle the full/empty flags and
the R/W strobes - and there also is a half full flag).

Dimiter

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Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
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