Clock problem? Altera Stratix-II ES and MP

Hi, all.  This is Tomoya greeting from Japan.

I would like to hear about Altera Stratix-II ES(engineering
sample)/MP(mass production) differences.

Here is background of our isse (we're facing);
We'd made three DDR evaluation boards using Altera Stratix-II
EP2S180/130.
It has DDR interface, DDR memories, and many IOs (GPIO:  General
purpose IO).  At first, we used EP2S180/130ES (engineering sample,
working sample) because of delivery.  It worked well.  DDR worked well
and GPIO ran at 200 MHz (or more) data communication speed between one
board to another board (board to board).

After that, we'are now making same evaluation set.  We use same PCB
bare board, same devices/parts ... only differences are that we used
EP2S180/130MS (mass production. Of course, same speed grade!).

However, the new one does not work well.   It works when we drop its
speed (from 200 to 150 MHz).
We're now guessing it has clock problem.   Especially,  FPGA internal
PLL.

Does anyone has had/faced same issue?
Does anyone knows any differences between ES and MP of EP2S180/130?

If you have any issue/information about these, let me know.  It helps
our work and of cource I would like to post it for your progresses.

Best regards,
---
Tomoya  <http://www.accverinos.jp/english/english.html>

Hello Tomoya-san,
We have an errata sheet published on
www.altera.com/literature/lit-stx2.jsp which shows the differences
between the ES and production devices. There's nothing there that is
directly connected to DDR memory interfaces, but I suggest that you
take a look and see if anything in your design is related to these
errata.

Of course your bigger question is "How can I make a DDR interface
work?" We have various literature, IP, and development kits on DDR
memory (also DDR2), so there's some resources there to help you in the
debug process. We have many customers using these memories so in
general the Altera device can implement the interface.
http://www.altera.com/technology/memory/sdram/mem-ddr_sdram.html
http://www.altera.com/technology/memory/dram/ddr2/mem-ddr2.html

Often when two seemingly similar parts behave differently, there may be
a subtle timing problem, and a part being a little faster or slower
than the other can cause a problem. Particularly with DDR, where
there's the added complication of the round trip where the FPGA drives
the clock of the DDR memory, so the data coming back to the FPGA must
be resynchronized. The literature I cited above has some information on
how to implement this.

Another source of timing problems is board power supply - we've seen
some cases where the IR drop of a connector sourcing power to the board
causes the FPGA's VCC to be below spec, which slows it down. Another
good thing to check.

If you think the PLL is a cause here, you could check the jitter on the
output of the ES part and the production device. But that's usually
pretty robust.

Another good tool (in case you don't know about it) is SignalTap, which
lets you probe the interior design of the FPGA and view the results on
your PC.

I hope that these suggestions help. They are pretty general but will
give you a good starting point.

Sincerely,
Greg Steinke
Altera Corporation

Greg-san, thak you for good comment.

>From the interface point of view,  DDR interfaces (there are two
DDR-200/400 interfaces on the evaluation board) are worked well
(DDR-200/400 runs on the both board, old and new).  The DDR module and
its interface runs under DCM.  Then, such clock jittar  (that Greg-san
suggested) will be cancelled (is not seen),  I guess (maybe).   The
only difference behavior that we had faced is, data communication.
Our board has total 750 general purpose IOs (these are 2.5 Volt
single-ended interface).  These interface does not run under DCM.
These are driven by the system clock (is generated by the FPGA internal
PLL).   The old one runs at 250 MHz (or more) speed.  But, the new one
runs at 150 MHz.   So, 40% down.   Therefore, I have such question (the
original question).

Anyway, we'll check the clock characteristics.  Especially, clock
jittar.

Thank you for good advice.  And I'm waiting for any other comments
about this issue.
Best regards,
---
Tomoya Kaku <URL:  http://www.accverinos.jp>
 Yokohma R&D Center, Verification System Development Division,
SK-Electronics CO., LTD